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drm/amdgpu: fix JPEG v4.0.5 queue reset failure in DPG mode

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Like jpeg_v5_0_0, in DPG mode the ring reset path only clears the
JPEG_PG_MODE bit and never resets a hung JRBC, so the post-reset ring test
times out and the driver falls back to a full MODE1 reset.

Temporarily force the static power-gating path during the reset so the
stop/start sequence power-cycles the JPEG block (JMI soft reset + power
off/on), matching the jpeg_v4_0 reset.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 75a308eef4)
Cc: stable@vger.kernel.org
This commit is contained in:
Jesse Zhang
2026-07-29 16:57:08 +08:00
committed by Alex Deucher
parent c87801f545
commit 4301e60e40
1 changed files with 17 additions and 4 deletions
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21
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
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@@ -772,15 +772,28 @@ static int jpeg_v4_0_5_ring_reset(struct amdgpu_ring *ring,
unsigned int vmid,
struct amdgpu_fence *timedout_fence)
{
struct amdgpu_device *adev = ring->adev;
u32 pg_flags = adev->pg_flags;
int r;
amdgpu_ring_reset_helper_begin(ring, timedout_fence);
r = jpeg_v4_0_5_stop(ring->adev);
if (r)
return r;
r = jpeg_v4_0_5_start(ring->adev);
/*
* The DPG stop path only clears the JPEG_PG_MODE bit and never resets a
* hung JRBC, so the post-reset ring test times out and the driver falls
* back to a full MODE1 reset. Temporarily force the static power-gating
* path so the stop/start sequence actually power-cycles the JPEG block
* (JMI soft reset + static power off/on), matching the working jpeg_v4_0
* reset.
*/
adev->pg_flags &= ~AMD_PG_SUPPORT_JPEG_DPG;
r = jpeg_v4_0_5_stop(adev);
if (!r)
r = jpeg_v4_0_5_start(adev);
adev->pg_flags = pg_flags;
if (r)
return r;
return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}