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arm64: dts: qcom: x1e80100: Add PCIe IOMMU

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x1e80100 has an SMMUv3 connected to PCIe which is normally controlled by
Gunyah and is thus transparent to the OS. However if we boot Linux in
EL2, without Gunyah, we need to manage this IOMMU ourselves. To make
that easier, and since the hardware actually exists, just not "usually"
managed by Linux, describe it in the dts as "reserved".

Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Link: https://lore.kernel.org/r/20250503-sc-el2-overlays-v2-4-24e9b4572e15@trvn.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Nikita Travkin
2025-05-03 15:39:31 +05:00
committed by Bjorn Andersson
parent 263780f318
commit 428f95f41f
1 changed files with 14 additions and 0 deletions
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14
arch/arm64/boot/dts/qcom/x1e80100.dtsi
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@@ -7940,6 +7940,20 @@ apps_smmu: iommu@15000000 {
dma-coherent;
};
pcie_smmu: iommu@15400000 {
compatible = "arm,smmu-v3";
reg = <0 0x15400000 0 0x80000>;
#iommu-cells = <1>;
interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq",
"gerror",
"cmdq-sync";
dma-coherent;
status = "reserved"; /* Controlled by Gunyah. */
};
intc: interrupt-controller@17000000 {
compatible = "arm,gic-v3";
reg = <0 0x17000000 0 0x10000>, /* GICD */