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net: ngbe: specify IRQ vector when the number of VFs is 7
For NGBE devices, the queue number is limited to be 1 when SRIOV is
enabled. In this case, IRQ vector[0] is used for MISC and vector[1] is
used for queue, based on the previous patches. But for the hardware
design, the IRQ vector[1] must be allocated for use by the VF[6] when
the number of VFs is 7. So the IRQ vector[0] should be shared for PF
MISC and QUEUE interrupts.
+-----------+----------------------+
| Vector | Assigned To |
+-----------+----------------------+
| Vector 0 | PF MISC and QUEUE |
| Vector 1 | VF 6 |
| Vector 2 | VF 5 |
| Vector 3 | VF 4 |
| Vector 4 | VF 3 |
| Vector 5 | VF 2 |
| Vector 6 | VF 1 |
| Vector 7 | VF 0 |
+-----------+----------------------+
Minimize code modifications, only adjust the IRQ vector number for this
case.
Fixes: 877253d2cb ("net: ngbe: add sriov function support")
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
Reviewed-by: Larysa Zaremba <larysa.zaremba@intel.com>
Link: https://patch.msgid.link/20250701063030.59340-4-jiawenwu@trustnetic.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
@@ -1795,6 +1795,13 @@ static int wx_acquire_msix_vectors(struct wx *wx)
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wx->msix_entry->entry = nvecs;
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wx->msix_entry->vector = pci_irq_vector(wx->pdev, nvecs);
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if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags)) {
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wx->msix_entry->entry = 0;
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wx->msix_entry->vector = pci_irq_vector(wx->pdev, 0);
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wx->msix_q_entries[0].entry = 0;
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wx->msix_q_entries[0].vector = pci_irq_vector(wx->pdev, 1);
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}
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return 0;
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}
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@@ -2293,6 +2300,8 @@ static void wx_set_ivar(struct wx *wx, s8 direction,
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if (direction == -1) {
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/* other causes */
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if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags))
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msix_vector = 0;
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msix_vector |= WX_PX_IVAR_ALLOC_VAL;
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index = 0;
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ivar = rd32(wx, WX_PX_MISC_IVAR);
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@@ -64,6 +64,7 @@ static void wx_sriov_clear_data(struct wx *wx)
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wr32m(wx, WX_PSR_VM_CTL, WX_PSR_VM_CTL_POOL_MASK, 0);
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wx->ring_feature[RING_F_VMDQ].offset = 0;
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clear_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags);
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clear_bit(WX_FLAG_SRIOV_ENABLED, wx->flags);
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/* Disable VMDq flag so device will be set in NM mode */
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if (wx->ring_feature[RING_F_VMDQ].limit == 1)
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@@ -78,6 +79,9 @@ static int __wx_enable_sriov(struct wx *wx, u8 num_vfs)
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set_bit(WX_FLAG_SRIOV_ENABLED, wx->flags);
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dev_info(&wx->pdev->dev, "SR-IOV enabled with %d VFs\n", num_vfs);
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if (num_vfs == 7 && wx->mac.type == wx_mac_em)
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set_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags);
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/* Enable VMDq flag so device will be set in VM mode */
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set_bit(WX_FLAG_VMDQ_ENABLED, wx->flags);
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if (!wx->ring_feature[RING_F_VMDQ].limit)
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@@ -1191,6 +1191,7 @@ enum wx_pf_flags {
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WX_FLAG_VMDQ_ENABLED,
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WX_FLAG_VLAN_PROMISC,
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WX_FLAG_SRIOV_ENABLED,
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WX_FLAG_IRQ_VECTOR_SHARED,
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WX_FLAG_FDIR_CAPABLE,
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WX_FLAG_FDIR_HASH,
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WX_FLAG_FDIR_PERFECT,
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@@ -286,7 +286,7 @@ static int ngbe_request_msix_irqs(struct wx *wx)
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* for queue. But when num_vfs == 7, vector[1] is assigned to vf6.
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* Misc and queue should reuse interrupt vector[0].
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*/
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if (wx->num_vfs == 7)
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if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags))
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err = request_irq(wx->msix_entry->vector,
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ngbe_misc_and_queue, 0, netdev->name, wx);
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else
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@@ -87,7 +87,7 @@
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#define NGBE_PX_MISC_IC_TIMESYNC BIT(11) /* time sync */
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#define NGBE_INTR_ALL 0x1FF
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#define NGBE_INTR_MISC(A) BIT((A)->num_q_vectors)
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#define NGBE_INTR_MISC(A) BIT((A)->msix_entry->entry)
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#define NGBE_PHY_CONFIG(reg_offset) (0x14000 + ((reg_offset) * 4))
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#define NGBE_CFG_LAN_SPEED 0x14440
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