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dma: fsl_raid: set final bit via fill_cfd_frame() argument

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The final-frame bit is now passed as the "final" argument of
fill_cfd_frame() (as fsl_re_prep_dma_memcpy already did) and set in CPU
order before the single cpu_to_be32() store, replacing the previous
read-modify-write of the __be32 efrl32 field.

Assisted-by: opencode:hy3-free
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260716202949.677290-3-rosenp@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Rosen Penev
2026-07-16 13:29:47 -07:00
committed by Vinod Koul
parent faa4ddedab
commit 416e9fd205
1 changed files with 8 additions and 8 deletions
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16
drivers/dma/fsl_raid.c
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@@ -375,11 +375,11 @@ static struct dma_async_tx_descriptor *fsl_re_prep_dma_genq(
for (i = 2, j = 0; j < save_src_cnt; i++, j++)
fill_cfd_frame(cf, i, len, src[j], 0);
/* Fill the last frame and mark it final */
if (cont_q)
fill_cfd_frame(cf, i++, len, dest, 0);
/* Setting the final bit in the last source buffer frame in CFD */
cf[i - 1].efrl32 |= 1 << FSL_RE_CF_FINAL_SHIFT;
fill_cfd_frame(cf, i, len, dest, 1);
else
fill_cfd_frame(cf, i - 1, len, src[j - 1], 1);
return &desc->async_tx;
}
@@ -505,16 +505,16 @@ static struct dma_async_tx_descriptor *fsl_re_prep_dma_pq(
p[save_src_cnt + 2] = 1;
fill_cfd_frame(cf, i++, len, dest[0], 0);
fill_cfd_frame(cf, i++, len, dest[1], 0);
fill_cfd_frame(cf, i++, len, dest[1], 0);
fill_cfd_frame(cf, i++, len, dest[1], 1);
} else {
dev_err(re_chan->dev, "PQ tx continuation error!\n");
return NULL;
}
} else {
/* Mark the last source buffer frame final */
fill_cfd_frame(cf, i - 1, len, src[j - 1], 1);
}
/* Setting the final bit in the last source buffer frame in CFD */
cf[i - 1].efrl32 |= 1 << FSL_RE_CF_FINAL_SHIFT;
return &desc->async_tx;
}