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arm64: dts: qcom: sm8550: add iris DT node

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Add DT entries for the sm8550 iris decoder.

Since the firmware is required to be signed, only enable
on Qualcomm development boards where the firmware is
publicly distributed.

Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250509-topic-sm8x50-upstream-iris-8550-dt-v4-1-22ced9179da3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Dikshita Agarwal
2025-05-09 17:31:24 +02:00
committed by Bjorn Andersson
parent cd81339e68
commit 41661853ae
4 changed files with 93 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/qcom/sm8550-hdk.dts
View File

@@ -945,6 +945,10 @@ &ipa {
status = "okay";
};
&iris {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};

4
arch/arm64/boot/dts/qcom/sm8550-mtp.dts
View File

@@ -672,6 +672,10 @@ fsa4480_sbu_mux: endpoint {
};
};
&iris {
status = "okay";
};
&lpass_tlmm {
spkr_1_sd_n_active: spkr-1-sd-n-active-state {
pins = "gpio17";

4
arch/arm64/boot/dts/qcom/sm8550-qrd.dts
View File

@@ -779,6 +779,10 @@ &ipa {
status = "okay";
};
&iris {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};

81
arch/arm64/boot/dts/qcom/sm8550.dtsi
View File

@@ -3221,6 +3221,87 @@ opp-202000000 {
};
};
iris: video-codec@aa00000 {
compatible = "qcom,sm8550-iris";
reg = <0 0x0aa00000 0 0xf0000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
<&videocc VIDEO_CC_MVS0_GDSC>,
<&rpmhpd RPMHPD_MXC>,
<&rpmhpd RPMHPD_MMCX>;
power-domain-names = "venus",
"vcodec0",
"mxc",
"mmcx";
operating-points-v2 = <&iris_opp_table>;
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
<&videocc VIDEO_CC_MVS0C_CLK>,
<&videocc VIDEO_CC_MVS0_CLK>;
clock-names = "iface",
"core",
"vcodec0_core";
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "cpu-cfg",
"video-mem";
memory-region = <&video_mem>;
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
reset-names = "bus";
iommus = <&apps_smmu 0x1940 0>,
<&apps_smmu 0x1947 0>;
dma-coherent;
/*
* IRIS firmware is signed by vendors, only
* enable in boards where the proper signed firmware
* is available.
*/
status = "disabled";
iris_opp_table: opp-table {
compatible = "operating-points-v2";
opp-240000000 {
opp-hz = /bits/ 64 <240000000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_low_svs>;
};
opp-338000000 {
opp-hz = /bits/ 64 <338000000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_svs>;
};
opp-366000000 {
opp-hz = /bits/ 64 <366000000>;
required-opps = <&rpmhpd_opp_svs_l1>,
<&rpmhpd_opp_svs_l1>;
};
opp-444000000 {
opp-hz = /bits/ 64 <444000000>;
required-opps = <&rpmhpd_opp_nom>,
<&rpmhpd_opp_nom>;
};
opp-533333334 {
opp-hz = /bits/ 64 <533333334>;
required-opps = <&rpmhpd_opp_turbo>,
<&rpmhpd_opp_turbo>;
};
};
};
videocc: clock-controller@aaf0000 {
compatible = "qcom,sm8550-videocc";
reg = <0 0x0aaf0000 0 0x10000>;