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media: iris: Add hardware power on/off ops for X1P42100

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On X1P42100 the Iris block has an extra BSE clock. Wire this clock into
the power on/off sequence.

The BSE clock is used to drive the Bin Stream Engine, which is a sub-block
of the video codec hardware responsible for bitstream-level processing. It
is required to be enabled separately from the core clock to ensure proper
codec operation.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
This commit is contained in:
Wangao Wang
2026-05-29 15:34:59 +08:00
committed by Bryan O'Donoghue
parent d1c9f40f76
commit 4147ffa3d9
1 changed files with 8 additions and 1 deletions
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9
drivers/media/platform/qcom/iris/iris_vpu_common.c
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@@ -224,6 +224,7 @@ void iris_vpu_power_off_hw(struct iris_core *core)
{
dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false);
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
iris_disable_unprepare_clock(core, IRIS_HW_CLK);
}
@@ -292,12 +293,18 @@ int iris_vpu_power_on_hw(struct iris_core *core)
if (ret && ret != -ENOENT)
goto err_disable_hw_clock;
ret = iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK);
if (ret && ret != -ENOENT)
goto err_disable_hw_ahb_clock;
ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);
if (ret)
goto err_disable_hw_ahb_clock;
goto err_disable_bse_hw_clock;
return 0;
err_disable_bse_hw_clock:
iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
err_disable_hw_ahb_clock:
iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
err_disable_hw_clock: