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Merge tag '20220323085010.1753493-4-dmitry.baryshkov@linaro.org' into clk-for-5.19

Browse Source 
v5.18-rc1 +
20220323085010.1753493-2-dmitry.baryshkov@linaro.org +
20220323085010.1753493-3-dmitry.baryshkov@linaro.org +
20220323085010.1753493-4-dmitry.baryshkov@linaro.org
This commit is contained in:
Bjorn Andersson
2022-04-12 13:41:27 -05:00
parent 3123109284 a9ed9e2bf7
commit 41219ff601
4 changed files with 89 additions and 4 deletions
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78
drivers/clk/qcom/clk-regmap-mux.c
View File

@@ -49,9 +49,87 @@ static int mux_set_parent(struct clk_hw *hw, u8 index)
return regmap_update_bits(clkr->regmap, mux->reg, mask, val);
}
static u8 mux_safe_get_parent(struct clk_hw *hw)
{
struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
unsigned int val;
if (clk_hw_is_enabled(hw))
return mux_get_parent(hw);
val = mux->stored_parent_cfg;
if (mux->parent_map)
return qcom_find_cfg_index(hw, mux->parent_map, val);
return val;
}
static int mux_safe_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
if (clk_hw_is_enabled(hw))
return mux_set_parent(hw, index);
if (mux->parent_map)
index = mux->parent_map[index].cfg;
mux->stored_parent_cfg = index;
return 0;
}
static void mux_safe_disable(struct clk_hw *hw)
{
struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
struct clk_regmap *clkr = to_clk_regmap(hw);
unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
unsigned int val;
regmap_read(clkr->regmap, mux->reg, &val);
mux->stored_parent_cfg = (val & mask) >> mux->shift;
val = mux->safe_src_parent;
if (mux->parent_map) {
int index = qcom_find_src_index(hw, mux->parent_map, val);
if (WARN_ON(index < 0))
return;
val = mux->parent_map[index].cfg;
}
val <<= mux->shift;
regmap_update_bits(clkr->regmap, mux->reg, mask, val);
}
static int mux_safe_enable(struct clk_hw *hw)
{
struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
struct clk_regmap *clkr = to_clk_regmap(hw);
unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
unsigned int val;
val = mux->stored_parent_cfg;
val <<= mux->shift;
return regmap_update_bits(clkr->regmap, mux->reg, mask, val);
}
const struct clk_ops clk_regmap_mux_closest_ops = {
.get_parent = mux_get_parent,
.set_parent = mux_set_parent,
.determine_rate = __clk_mux_determine_rate_closest,
};
EXPORT_SYMBOL_GPL(clk_regmap_mux_closest_ops);
const struct clk_ops clk_regmap_mux_safe_ops = {
.enable = mux_safe_enable,
.disable = mux_safe_disable,
.get_parent = mux_safe_get_parent,
.set_parent = mux_safe_set_parent,
.determine_rate = __clk_mux_determine_rate_closest,
};
EXPORT_SYMBOL_GPL(clk_regmap_mux_safe_ops);

3
drivers/clk/qcom/clk-regmap-mux.h
View File

@@ -14,10 +14,13 @@ struct clk_regmap_mux {
u32 reg;
u32 shift;
u32 width;
u8 safe_src_parent;
u8 stored_parent_cfg;
const struct parent_map *parent_map;
struct clk_regmap clkr;
};
extern const struct clk_ops clk_regmap_mux_closest_ops;
extern const struct clk_ops clk_regmap_mux_safe_ops;
#endif

6
drivers/clk/qcom/gcc-sc7280.c
View File

@@ -373,13 +373,14 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x6b054,
.shift = 0,
.width = 2,
.safe_src_parent = P_BI_TCXO,
.parent_map = gcc_parent_map_6,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_regmap_mux_closest_ops,
.ops = &clk_regmap_mux_safe_ops,
},
},
};
@@ -388,13 +389,14 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
.reg = 0x8d054,
.shift = 0,
.width = 2,
.safe_src_parent = P_BI_TCXO,
.parent_map = gcc_parent_map_7,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_regmap_mux_closest_ops,
.ops = &clk_regmap_mux_safe_ops,
},
},
};

6
drivers/clk/qcom/gcc-sm8450.c
View File

@@ -243,13 +243,14 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x7b060,
.shift = 0,
.width = 2,
.safe_src_parent = P_BI_TCXO,
.parent_map = gcc_parent_map_4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_regmap_mux_closest_ops,
.ops = &clk_regmap_mux_safe_ops,
},
},
};
@@ -273,13 +274,14 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
.reg = 0x9d064,
.shift = 0,
.width = 2,
.safe_src_parent = P_BI_TCXO,
.parent_map = gcc_parent_map_6,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_regmap_mux_closest_ops,
.ops = &clk_regmap_mux_safe_ops,
},
},
};