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arm64: dts: amlogic: gx: assign the MMC signal clocks

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The amlogic MMC driver operate with the assumption that MMC clock
is configured to provide 24MHz. It uses this path for low
rates such as 400kHz.

Assign the clocks to make sure they are properly configured

Fixes: 50662499f9 ("ARM64: dts: meson-gx: Use correct mmc clock source 0")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260114-amlogic-mmc-clocks-followup-v1-4-a999fafbe0aa@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
This commit is contained in:
Jerome Brunet
2026-01-14 18:08:51 +01:00
committed by Neil Armstrong
parent 13d3fe2318
commit 4067065590
2 changed files with 18 additions and 0 deletions
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9
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View File

@@ -824,6 +824,9 @@ &sd_emmc_a {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>;
assigned-clock-rates = <24000000>;
};
&sd_emmc_b {
@@ -832,6 +835,9 @@ &sd_emmc_b {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>;
assigned-clock-rates = <24000000>;
};
&sd_emmc_c {
@@ -840,6 +846,9 @@ &sd_emmc_c {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
assigned-clock-rates = <24000000>;
};
&simplefb_hdmi {

9
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@@ -894,6 +894,9 @@ &sd_emmc_a {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>;
assigned-clock-rates = <24000000>;
};
&sd_emmc_b {
@@ -902,6 +905,9 @@ &sd_emmc_b {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>;
assigned-clock-rates = <24000000>;
};
&sd_emmc_c {
@@ -910,6 +916,9 @@ &sd_emmc_c {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
assigned-clock-rates = <24000000>;
};
&simplefb_hdmi {