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Merge tag 'hisi-arm64-dt-for-6.10' of https://github.com/hisilicon/linux-hisi into soc/dt

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ARM64: DT: HiSilicon ARM64 DT updates for v6.10

- Move non-MMIO node out of soc for the hip05, hip06 and hip07 SoC
- Miscellaneous fixes and improvements like correcting unit addresses and
missing reg

* tag 'hisi-arm64-dt-for-6.10' of https://github.com/hisilicon/linux-hisi:
  arm64: dts: hisilicon: hi6220: correct tsensor unit addresses
  arm64: dts: hisilicon: hi6220-hikey: drop unit addresses from fixed regulators
  arm64: dts: hisilicon: hi6220-hikey: add missing port@0 reg
  arm64: dts: hisilicon: hip07: correct unit addresses
  arm64: dts: hisilicon: hip07: move non-MMIO node out of soc
  arm64: dts: hisilicon: hip06: correct unit addresses
  arm64: dts: hisilicon: hip06: move non-MMIO node out of soc
  arm64: dts: hisilicon: hip05-d02: correct local-bus unit addresses
  arm64: dts: hisilicon: hip05: move non-MMIO node out of soc

Link: https://lore.kernel.org/r/662A4115.9020805@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2024-04-29 10:33:10 +02:00
parent 5ac40fdde3 5cff113558
commit 405a7cd986
6 changed files with 99 additions and 98 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
View File

@@ -82,7 +82,7 @@ reboot-mode {
};
};
reg_sys_5v: regulator@0 {
reg_sys_5v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "SYS_5V";
regulator-min-microvolt = <5000000>;
@@ -91,7 +91,7 @@ reg_sys_5v: regulator@0 {
regulator-always-on;
};
reg_vdd_3v3: regulator@1 {
reg_vdd_3v3: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3";
regulator-min-microvolt = <3300000>;
@@ -101,7 +101,7 @@ reg_vdd_3v3: regulator@1 {
vin-supply = <&reg_sys_5v>;
};
reg_5v_hub: regulator@2 {
reg_5v_hub: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "5V_HUB";
regulator-min-microvolt = <5000000>;
@@ -514,6 +514,7 @@ ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7533_in: endpoint {
remote-endpoint = <&dsi_out0>;
};

2
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View File

@@ -852,7 +852,7 @@ watchdog0: watchdog@f8005000 {
clock-names = "wdog_clk", "apb_pclk";
};
tsensor: tsensor@0,f7030700 {
tsensor: tsensor@f7030700 {
compatible = "hisilicon,tsensor";
reg = <0x0 0xf7030700 0x0 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

4
arch/arm64/boot/dts/hisilicon/hip05-d02.dts
View File

@@ -54,7 +54,7 @@ &lbc {
ranges = <0 0 0x0 0x90000000 0x08000000>,
<1 0 0x0 0x98000000 0x08000000>;
nor-flash@0,0 {
nor-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "numonyx,js28f00a", "cfi-flash";
@@ -75,7 +75,7 @@ partition@1000000 {
};
};
cpld@1,0 {
cpld@100000000 {
compatible = "hisilicon,hip05-cpld";
reg = <1 0x0 0x100>;
};

12
arch/arm64/boot/dts/hisilicon/hip05.dtsi
View File

@@ -279,6 +279,12 @@ its_dsa: msi-controller@c6000000 {
};
};
refclk200mhz: refclk200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
@@ -298,12 +304,6 @@ soc {
#size-cells = <2>;
ranges;
refclk200mhz: refclk200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart0: serial@80300000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x80300000 0x0 0x10000>;

88
arch/arm64/boot/dts/hisilicon/hip06.dtsi
View File

@@ -258,6 +258,48 @@ its_dsa: msi-controller@c6000000 {
};
};
eth2: ethernet-0 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <0>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth3: ethernet-1 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <1>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth0: ethernet-4 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <4>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth1: ethernet-5 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <5>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
refclk: refclk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
@@ -374,12 +416,6 @@ uart0: serial@2f8 {
};
};
refclk: refclk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
};
usb_ohci: usb@a7030000 {
compatible = "generic-ohci";
reg = <0x0 0xa7030000 0x0 0x10000>;
@@ -436,7 +472,7 @@ phy1: ethernet-phy@1 {
};
};
dsaf0: dsa@c7000000 {
dsaf0: dsa@c5000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "hisilicon,hns-dsaf-v2";
@@ -570,42 +606,6 @@ port@5 {
};
};
eth0: ethernet-4 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <4>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth1: ethernet-5 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <5>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth2: ethernet-0 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <0>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth3: ethernet-1 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <1>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
sas0: sas@c3000000 {
compatible = "hisilicon,hip06-sas-v2";
reg = <0 0xc3000000 0 0x10000>;
@@ -733,7 +733,7 @@ sas2: sas@a3000000 {
status = "disabled";
};
pcie0: pcie@a0090000 {
pcie0: pcie@b0000000 {
compatible = "hisilicon,hip06-pcie-ecam";
reg = <0 0xb0000000 0 0x2000000>,
<0 0xa0090000 0 0x10000>;

84
arch/arm64/boot/dts/hisilicon/hip07.dtsi
View File

@@ -1013,6 +1013,42 @@ p1_its_dsa_b: msi-controller@408c6000000 {
};
};
eth0: ethernet-0 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <4>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth1: ethernet-1 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <5>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth2: ethernet-2 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <0>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth3: ethernet-3 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <1>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
@@ -1343,7 +1379,7 @@ phy1: ethernet-phy@1 {
};
};
dsaf0: dsa@c7000000 {
dsaf0: dsa@c5000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "hisilicon,hns-dsaf-v2";
@@ -1483,42 +1519,6 @@ port@5 {
};
};
eth0: ethernet@4 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <4>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth1: ethernet@5 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <5>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth2: ethernet@0 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <0>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth3: ethernet@1 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <1>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
infiniband@c4000000 {
compatible = "hisilicon,hns-roce-v1";
reg = <0x0 0xc4000000 0x0 0x100000>;
@@ -1724,7 +1724,7 @@ sas2: sas@a3000000 {
status = "disabled";
};
p0_pcie2_a: pcie@a00a0000 {
p0_pcie2_a: pcie@af800000 {
compatible = "hisilicon,hip07-pcie-ecam";
reg = <0 0xaf800000 0 0x800000>,
<0 0xa00a0000 0 0x10000>;
@@ -1745,7 +1745,7 @@ p0_pcie2_a: pcie@a00a0000 {
0x0 0 0 4 &mbigen_pcie2_a 671 4>;
status = "disabled";
};
p0_sec_a: crypto@d2000000 {
p0_sec_a: crypto@d0000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x0 0xd0000000 0x0 0x10000>,
<0x0 0xd2000000 0x0 0x10000>,
@@ -1786,7 +1786,7 @@ p0_sec_a: crypto@d2000000 {
<605 1>, <606 4>,
<607 1>, <608 4>;
};
p0_sec_b: crypto@8,d2000000 {
p0_sec_b: crypto@8d0000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x8 0xd0000000 0x0 0x10000>,
<0x8 0xd2000000 0x0 0x10000>,
@@ -1827,7 +1827,7 @@ p0_sec_b: crypto@8,d2000000 {
<605 1>, <606 4>,
<607 1>, <608 4>;
};
p1_sec_a: crypto@400,d2000000 {
p1_sec_a: crypto@400d0000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x400 0xd0000000 0x0 0x10000>,
<0x400 0xd2000000 0x0 0x10000>,
@@ -1868,7 +1868,7 @@ p1_sec_a: crypto@400,d2000000 {
<605 1>, <606 4>,
<607 1>, <608 4>;
};
p1_sec_b: crypto@408,d2000000 {
p1_sec_b: crypto@408d0000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x408 0xd0000000 0x0 0x10000>,
<0x408 0xd2000000 0x0 0x10000>,