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net: hibmcge: configure FIFO thresholds according to the MAC controller documentation

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Configure FIFO thresholds according to the MAC controller documentation

Signed-off-by: Jijie Shao <shaojijie@huawei.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20250702125716.2875169-4-shaojijie@huawei.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jijie Shao
2025-07-02 20:57:16 +08:00
committed by Jakub Kicinski
parent 1051404bab
commit 401581f286
2 changed files with 55 additions and 0 deletions
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49
drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c
View File

@@ -18,6 +18,13 @@
#define HBG_ENDIAN_CTRL_LE_DATA_BE 0x0
#define HBG_PCU_FRAME_LEN_PLUS 4
#define HBG_FIFO_TX_FULL_THRSLD 0x3F0
#define HBG_FIFO_TX_EMPTY_THRSLD 0x1F0
#define HBG_FIFO_RX_FULL_THRSLD 0x240
#define HBG_FIFO_RX_EMPTY_THRSLD 0x190
#define HBG_CFG_FIFO_FULL_THRSLD 0x10
#define HBG_CFG_FIFO_EMPTY_THRSLD 0x01
static bool hbg_hw_spec_is_valid(struct hbg_priv *priv)
{
return hbg_reg_read(priv, HBG_REG_SPEC_VALID_ADDR) &&
@@ -272,6 +279,41 @@ void hbg_hw_set_rx_pause_mac_addr(struct hbg_priv *priv, u64 mac_addr)
hbg_reg_write64(priv, HBG_REG_FD_FC_ADDR_LOW_ADDR, mac_addr);
}
static void hbg_hw_set_fifo_thrsld(struct hbg_priv *priv,
u32 full, u32 empty, enum hbg_dir dir)
{
u32 value = 0;
value |= FIELD_PREP(HBG_REG_FIFO_THRSLD_FULL_M, full);
value |= FIELD_PREP(HBG_REG_FIFO_THRSLD_EMPTY_M, empty);
if (dir & HBG_DIR_TX)
hbg_reg_write(priv, HBG_REG_TX_FIFO_THRSLD_ADDR, value);
if (dir & HBG_DIR_RX)
hbg_reg_write(priv, HBG_REG_RX_FIFO_THRSLD_ADDR, value);
}
static void hbg_hw_set_cfg_fifo_thrsld(struct hbg_priv *priv,
u32 full, u32 empty, enum hbg_dir dir)
{
u32 value;
value = hbg_reg_read(priv, HBG_REG_CFG_FIFO_THRSLD_ADDR);
if (dir & HBG_DIR_TX) {
value |= FIELD_PREP(HBG_REG_CFG_FIFO_THRSLD_TX_FULL_M, full);
value |= FIELD_PREP(HBG_REG_CFG_FIFO_THRSLD_TX_EMPTY_M, empty);
}
if (dir & HBG_DIR_RX) {
value |= FIELD_PREP(HBG_REG_CFG_FIFO_THRSLD_RX_FULL_M, full);
value |= FIELD_PREP(HBG_REG_CFG_FIFO_THRSLD_RX_EMPTY_M, empty);
}
hbg_reg_write(priv, HBG_REG_CFG_FIFO_THRSLD_ADDR, value);
}
static void hbg_hw_init_transmit_ctrl(struct hbg_priv *priv)
{
u32 ctrl = 0;
@@ -332,5 +374,12 @@ int hbg_hw_init(struct hbg_priv *priv)
hbg_hw_init_rx_control(priv);
hbg_hw_init_transmit_ctrl(priv);
hbg_hw_set_fifo_thrsld(priv, HBG_FIFO_TX_FULL_THRSLD,
HBG_FIFO_TX_EMPTY_THRSLD, HBG_DIR_TX);
hbg_hw_set_fifo_thrsld(priv, HBG_FIFO_RX_FULL_THRSLD,
HBG_FIFO_RX_EMPTY_THRSLD, HBG_DIR_RX);
hbg_hw_set_cfg_fifo_thrsld(priv, HBG_CFG_FIFO_FULL_THRSLD,
HBG_CFG_FIFO_EMPTY_THRSLD, HBG_DIR_TX_RX);
return 0;
}

6
drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h
View File

@@ -141,7 +141,13 @@
/* PCU */
#define HBG_REG_TX_FIFO_THRSLD_ADDR (HBG_REG_SGMII_BASE + 0x0420)
#define HBG_REG_RX_FIFO_THRSLD_ADDR (HBG_REG_SGMII_BASE + 0x0424)
#define HBG_REG_FIFO_THRSLD_FULL_M GENMASK(25, 16)
#define HBG_REG_FIFO_THRSLD_EMPTY_M GENMASK(9, 0)
#define HBG_REG_CFG_FIFO_THRSLD_ADDR (HBG_REG_SGMII_BASE + 0x0428)
#define HBG_REG_CFG_FIFO_THRSLD_TX_FULL_M GENMASK(31, 24)
#define HBG_REG_CFG_FIFO_THRSLD_TX_EMPTY_M GENMASK(23, 16)
#define HBG_REG_CFG_FIFO_THRSLD_RX_FULL_M GENMASK(15, 8)
#define HBG_REG_CFG_FIFO_THRSLD_RX_EMPTY_M GENMASK(7, 0)
#define HBG_REG_CF_INTRPT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x042C)
#define HBG_INT_MSK_WE_ERR_B BIT(31)
#define HBG_INT_MSK_RBREQ_ERR_B BIT(30)