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arm64: dts: renesas: r9a09g087: Add CANFD node

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Add support for the CANFD controller on the Renesas RZ/N2H Soc.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251224175204.3400062-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
2025-12-24 17:52:00 +00:00
committed by Geert Uytterhoeven
parent ff108a26c9
commit 3fcf1e255e
1 changed files with 31 additions and 0 deletions
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31
arch/arm64/boot/dts/renesas/r9a09g087.dtsi
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@@ -260,6 +260,37 @@ rspi3: spi@81007000 {
status = "disabled";
};
canfd: can@80040000 {
compatible = "renesas,r9a09g087-canfd", "renesas,r9a09g077-canfd";
reg = <0 0x80040000 0 0x20000>;
interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "g_err", "g_recc",
"ch0_err", "ch0_rec", "ch0_trx",
"ch1_err", "ch1_rec", "ch1_trx";
clocks = <&cpg CPG_MOD 310>,
<&cpg CPG_CORE R9A09G087_CLK_PCLKH>,
<&cpg CPG_CORE R9A09G087_PCLKCAN>;
clock-names = "fck", "ram_clk", "can_clk";
assigned-clocks = <&cpg CPG_CORE R9A09G087_PCLKCAN>;
assigned-clock-rates = <80000000>;
power-domains = <&cpg>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
wdt0: watchdog@80082000 {
compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
reg = <0 0x80082000 0 0x400>,