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drm/amdkfd: remove unused kfd_pm4_headers_diq header file
kfd_pm4_headers_diq.h header is a leftover from the old H/W debugger module support added on commitfbeb661bfa("drm/amdkfd: Add skeleton H/W debugger module support"). That implementation was removed after a while and the last file that included that header was removed on commit5bdd3eb253("drm/amdkfd: Remove unused old debugger implementation"). This patch removes the unused header file kfd_pm4_headers_diq.h Signed-off-by: Paulo Miguel Almeida <paulo.miguel.almeida.rodenas@gmail.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Paulo Miguel Almeida
committed by
Alex Deucher
Alex Deucher
parent
5468c36d62
commit
3f1a02ebee
@@ -1,291 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/*
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* Copyright 2014-2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef KFD_PM4_HEADERS_DIQ_H_
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#define KFD_PM4_HEADERS_DIQ_H_
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/*--------------------_INDIRECT_BUFFER-------------------- */
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#ifndef _PM4__INDIRECT_BUFFER_DEFINED
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#define _PM4__INDIRECT_BUFFER_DEFINED
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enum _INDIRECT_BUFFER_cache_policy_enum {
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cache_policy___indirect_buffer__lru = 0,
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cache_policy___indirect_buffer__stream = 1,
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cache_policy___indirect_buffer__bypass = 2
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};
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enum {
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IT_INDIRECT_BUFFER_PASID = 0x5C
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};
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struct pm4__indirect_buffer_pasid {
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union {
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union PM4_MES_TYPE_3_HEADER header; /* header */
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unsigned int ordinal1;
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};
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union {
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struct {
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unsigned int reserved1:2;
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unsigned int ib_base_lo:30;
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} bitfields2;
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unsigned int ordinal2;
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};
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union {
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struct {
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unsigned int ib_base_hi:16;
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unsigned int reserved2:16;
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} bitfields3;
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unsigned int ordinal3;
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};
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union {
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unsigned int control;
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unsigned int ordinal4;
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};
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union {
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struct {
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unsigned int pasid:10;
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unsigned int reserved4:22;
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} bitfields5;
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unsigned int ordinal5;
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};
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};
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#endif
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/*--------------------_RELEASE_MEM-------------------- */
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#ifndef _PM4__RELEASE_MEM_DEFINED
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#define _PM4__RELEASE_MEM_DEFINED
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enum _RELEASE_MEM_event_index_enum {
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event_index___release_mem__end_of_pipe = 5,
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event_index___release_mem__shader_done = 6
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};
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enum _RELEASE_MEM_cache_policy_enum {
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cache_policy___release_mem__lru = 0,
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cache_policy___release_mem__stream = 1,
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cache_policy___release_mem__bypass = 2
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};
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enum _RELEASE_MEM_dst_sel_enum {
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dst_sel___release_mem__memory_controller = 0,
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dst_sel___release_mem__tc_l2 = 1,
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dst_sel___release_mem__queue_write_pointer_register = 2,
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dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3
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};
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enum _RELEASE_MEM_int_sel_enum {
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int_sel___release_mem__none = 0,
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int_sel___release_mem__send_interrupt_only = 1,
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int_sel___release_mem__send_interrupt_after_write_confirm = 2,
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int_sel___release_mem__send_data_after_write_confirm = 3
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};
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enum _RELEASE_MEM_data_sel_enum {
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data_sel___release_mem__none = 0,
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data_sel___release_mem__send_32_bit_low = 1,
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data_sel___release_mem__send_64_bit_data = 2,
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data_sel___release_mem__send_gpu_clock_counter = 3,
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data_sel___release_mem__send_cp_perfcounter_hi_lo = 4,
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data_sel___release_mem__store_gds_data_to_memory = 5
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};
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struct pm4__release_mem {
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union {
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union PM4_MES_TYPE_3_HEADER header; /*header */
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unsigned int ordinal1;
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};
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union {
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struct {
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unsigned int event_type:6;
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unsigned int reserved1:2;
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enum _RELEASE_MEM_event_index_enum event_index:4;
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unsigned int tcl1_vol_action_ena:1;
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unsigned int tc_vol_action_ena:1;
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unsigned int reserved2:1;
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unsigned int tc_wb_action_ena:1;
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unsigned int tcl1_action_ena:1;
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unsigned int tc_action_ena:1;
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unsigned int reserved3:6;
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unsigned int atc:1;
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enum _RELEASE_MEM_cache_policy_enum cache_policy:2;
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unsigned int reserved4:5;
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} bitfields2;
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unsigned int ordinal2;
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};
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union {
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struct {
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unsigned int reserved5:16;
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enum _RELEASE_MEM_dst_sel_enum dst_sel:2;
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unsigned int reserved6:6;
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enum _RELEASE_MEM_int_sel_enum int_sel:3;
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unsigned int reserved7:2;
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enum _RELEASE_MEM_data_sel_enum data_sel:3;
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} bitfields3;
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unsigned int ordinal3;
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};
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union {
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struct {
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unsigned int reserved8:2;
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unsigned int address_lo_32b:30;
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} bitfields4;
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struct {
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unsigned int reserved9:3;
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unsigned int address_lo_64b:29;
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} bitfields5;
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unsigned int ordinal4;
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};
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unsigned int address_hi;
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unsigned int data_lo;
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unsigned int data_hi;
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};
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#endif
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/*--------------------_SET_CONFIG_REG-------------------- */
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#ifndef _PM4__SET_CONFIG_REG_DEFINED
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#define _PM4__SET_CONFIG_REG_DEFINED
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struct pm4__set_config_reg {
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union {
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union PM4_MES_TYPE_3_HEADER header; /*header */
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unsigned int ordinal1;
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};
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union {
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struct {
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unsigned int reg_offset:16;
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unsigned int reserved1:7;
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unsigned int vmid_shift:5;
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unsigned int insert_vmid:1;
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unsigned int reserved2:3;
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} bitfields2;
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unsigned int ordinal2;
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};
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unsigned int reg_data[1]; /*1..N of these fields */
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};
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#endif
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/*--------------------_WAIT_REG_MEM-------------------- */
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#ifndef _PM4__WAIT_REG_MEM_DEFINED
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#define _PM4__WAIT_REG_MEM_DEFINED
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enum _WAIT_REG_MEM_function_enum {
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function___wait_reg_mem__always_pass = 0,
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function___wait_reg_mem__less_than_ref_value = 1,
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function___wait_reg_mem__less_than_equal_to_the_ref_value = 2,
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function___wait_reg_mem__equal_to_the_reference_value = 3,
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function___wait_reg_mem__not_equal_reference_value = 4,
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function___wait_reg_mem__greater_than_or_equal_reference_value = 5,
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function___wait_reg_mem__greater_than_reference_value = 6,
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function___wait_reg_mem__reserved = 7
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};
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enum _WAIT_REG_MEM_mem_space_enum {
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mem_space___wait_reg_mem__register_space = 0,
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mem_space___wait_reg_mem__memory_space = 1
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};
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enum _WAIT_REG_MEM_operation_enum {
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operation___wait_reg_mem__wait_reg_mem = 0,
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operation___wait_reg_mem__wr_wait_wr_reg = 1
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};
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struct pm4__wait_reg_mem {
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union {
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union PM4_MES_TYPE_3_HEADER header; /*header */
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unsigned int ordinal1;
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};
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union {
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struct {
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enum _WAIT_REG_MEM_function_enum function:3;
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unsigned int reserved1:1;
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enum _WAIT_REG_MEM_mem_space_enum mem_space:2;
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enum _WAIT_REG_MEM_operation_enum operation:2;
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unsigned int reserved2:24;
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} bitfields2;
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unsigned int ordinal2;
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};
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union {
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struct {
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unsigned int reserved3:2;
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unsigned int memory_poll_addr_lo:30;
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} bitfields3;
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struct {
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unsigned int register_poll_addr:16;
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unsigned int reserved4:16;
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} bitfields4;
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struct {
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unsigned int register_write_addr:16;
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unsigned int reserved5:16;
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} bitfields5;
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unsigned int ordinal3;
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};
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union {
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struct {
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unsigned int poll_address_hi:16;
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unsigned int reserved6:16;
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} bitfields6;
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struct {
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unsigned int register_write_addr:16;
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unsigned int reserved7:16;
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} bitfields7;
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unsigned int ordinal4;
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};
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unsigned int reference;
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unsigned int mask;
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union {
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struct {
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unsigned int poll_interval:16;
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unsigned int reserved8:16;
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} bitfields8;
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unsigned int ordinal7;
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};
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};
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#endif
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#endif /* KFD_PM4_HEADERS_DIQ_H_ */
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