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drm/i915/display: Ensure phy is accessible on lfps configuration

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Ensure phy is accessible on lfps configuration by adding
intel_cx0_phy_transaction_begin/end around it.

Fixes: 9dc619680d ("drm/i915/display: Add function to configure LFPS sending")
Suggested-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20250722125618.1842615-4-jouni.hogander@intel.com
(cherry picked from commit cf433f94f1)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
This commit is contained in:
Jouni Högander
2025-07-22 15:56:17 +03:00
committed by Tvrtko Ursulin
parent c338923c4c
commit 3eb63578d8
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/i915/display/intel_cx0_phy.c
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@@ -3239,6 +3239,7 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
intel_wakeref_t wakeref;
int i;
u8 owned_lane_mask;
@@ -3247,6 +3248,9 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
return;
owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
wakeref = intel_cx0_phy_transaction_begin(encoder);
for (i = 0; i < 4; i++) {
int tx = i % 2 + 1;
u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
@@ -3258,6 +3262,8 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
CONTROL0_MAC_TRANSMIT_LFPS,
CONTROL0_MAC_TRANSMIT_LFPS, MB_WRITE_COMMITTED);
}
intel_cx0_phy_transaction_end(encoder, wakeref);
}
static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)