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Merge tag 'icc-6.19-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next

Browse Source 
Georgi writes:

interconnect changes for 6.19

This pull request contains the interconnect changes for the 6.19-rc1
merge window. The core and driver changes are listed below.

Core changes:
- kbps_to_icc() macro optimization

Driver changes:
- Switch all Qualcomm RPMh interconnect drivers to use the dynamic
  node IDs and drop support for non-dynamic ID allocation
- Add new driver and BWMON support for the Kaanapali SoC
- Add QoS support for the SM6350 SoC
- Add QoS support for the SA8775p SoC
- Fix missing link from SNOC_PNOC to the USB 2 on MSM8996 SoC that
  includes also a dts change that has been acked by the maintainer
- Drop the QPIC interconnect and BCM nodes for the SDX75 SoC, as these
  should be handled by the rpmh-clk driver
- Other misc fixes

Signed-off-by: Georgi Djakov <djakov@kernel.org>

* tag 'icc-6.19-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc: (40 commits)
  interconnect: qcom: sm6350: enable QoS configuration
  interconnect: qcom: sm6350: Remove empty BCM arrays
  interconnect: qcom: icc-rpmh: Get parent's regmap for nested NoCs
  dt-bindings: interconnect: qcom,sm6350-rpmh: Add clocks for QoS
  dt-bindings: interconnect: qcom-bwmon: Document Kaanapali BWMONs
  interconnect: qcom: icc-rpmh: drop support for non-dynamic IDS
  interconnect: qcom: sm8750: convert to dynamic IDs
  interconnect: qcom: sm8650: convert to dynamic IDs
  interconnect: qcom: sm8550: convert to dynamic IDs
  interconnect: qcom: sm8450: convert to dynamic IDs
  interconnect: qcom: sm8350: convert to dynamic IDs
  interconnect: qcom: sm8150: convert to dynamic IDs
  interconnect: qcom: sm7150: convert to dynamic IDs
  interconnect: qcom: sm6350: convert to dynamic IDs
  interconnect: qcom: sdx75: convert to dynamic IDs
  interconnect: qcom: sdx65: convert to dynamic IDs
  interconnect: qcom: sdx55: convert to dynamic IDs
  interconnect: qcom: sdm670: convert to dynamic IDs
  interconnect: qcom: sc7180: convert to dynamic IDs
  interconnect: qcom: sar2130p: convert to dynamic IDs
  ...
This commit is contained in:
Greg Kroah-Hartman
2025-11-24 17:35:12 +01:00
parent ac4b8282bb 60b52af082
commit 3e92fdae7f
62 changed files with 9632 additions and 10785 deletions
Download Patch File Download Diff File Expand all files Collapse all files

124
Documentation/devicetree/bindings/interconnect/qcom,kaanapali-rpmh.yaml Normal file
View File

@@ -0,0 +1,124 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,kaanapali-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on Kaanapali
maintainers:
- Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also: include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h
properties:
compatible:
enum:
- qcom,kaanapali-aggre-noc
- qcom,kaanapali-clk-virt
- qcom,kaanapali-cnoc-main
- qcom,kaanapali-cnoc-cfg
- qcom,kaanapali-gem-noc
- qcom,kaanapali-lpass-ag-noc
- qcom,kaanapali-lpass-lpiaon-noc
- qcom,kaanapali-lpass-lpicx-noc
- qcom,kaanapali-mc-virt
- qcom,kaanapali-mmss-noc
- qcom,kaanapali-nsp-noc
- qcom,kaanapali-pcie-anoc
- qcom,kaanapali-system-noc
reg:
maxItems: 1
clocks:
minItems: 2
maxItems: 3
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,kaanapali-clk-virt
- qcom,kaanapali-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
enum:
- qcom,kaanapali-pcie-anoc
then:
properties:
clocks:
items:
- description: aggre-NOC PCIe AXI clock
- description: cfg-NOC PCIe a-NOC AHB clock
- if:
properties:
compatible:
contains:
enum:
- qcom,kaanapali-aggre-noc
then:
properties:
clocks:
items:
- description: aggre UFS PHY AXI clock
- description: aggre USB3 PRIM AXI clock
- description: RPMH CC IPA clock
- if:
properties:
compatible:
contains:
enum:
- qcom,kaanapali-aggre-noc
- qcom,kaanapali-pcie-anoc
then:
required:
- clocks
else:
properties:
clocks: false
unevaluatedProperties: false
examples:
- |
clk_virt: interconnect-0 {
compatible = "qcom,kaanapali-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre_noc: interconnect@16e0000 {
compatible = "qcom,kaanapali-aggre-noc";
reg = <0x016e0000 0x42400>;
#interconnect-cells = <2>;
clocks = <&gcc_aggre_ufs_phy_axi_clk>,
<&gcc_aggre_usb3_prim_axi_clk>,
<&rpmhcc_ipa_clk>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

1
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
View File

@@ -25,6 +25,7 @@ properties:
- const: qcom,msm8998-bwmon # BWMON v4
- items:
- enum:
- qcom,kaanapali-cpu-bwmon
- qcom,qcm2290-cpu-bwmon
- qcom,qcs615-cpu-bwmon
- qcom,qcs8300-cpu-bwmon

52
Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml
View File

@@ -33,18 +33,66 @@ properties:
- qcom,sa8775p-pcie-anoc
- qcom,sa8775p-system-noc
reg:
maxItems: 1
clocks:
minItems: 2
maxItems: 5
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sa8775p-aggre1-noc
then:
properties:
clocks:
items:
- description: aggre UFS PHY AXI clock
- description: aggre QUP PRIM AXI clock
- description: aggre USB2 PRIM AXI clock
- description: aggre USB3 PRIM AXI clock
- description: aggre USB3 SEC AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sa8775p-aggre2-noc
then:
properties:
clocks:
items:
- description: aggre UFS CARD AXI clock
- description: RPMH CC IPA clock
unevaluatedProperties: false
examples:
- |
aggre1_noc: interconnect-aggre1-noc {
compatible = "qcom,sa8775p-aggre1-noc";
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
clk_virt: interconnect-clk-virt {
compatible = "qcom,sa8775p-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16c0000 {
compatible = "qcom,sa8775p-aggre1-noc";
reg = <0x016c0000 0x18080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>,
<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
};

65
Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
View File

@@ -12,9 +12,6 @@ maintainers:
description:
Qualcomm RPMh-based interconnect provider on SM6350.
allOf:
- $ref: qcom,rpmh-common.yaml#
properties:
compatible:
enum:
@@ -30,7 +27,9 @@ properties:
reg:
maxItems: 1
'#interconnect-cells': true
clocks:
minItems: 1
maxItems: 2
patternProperties:
'^interconnect-[a-z0-9\-]+$':
@@ -46,8 +45,6 @@ patternProperties:
- qcom,sm6350-clk-virt
- qcom,sm6350-compute-noc
'#interconnect-cells': true
required:
- compatible
@@ -57,10 +54,54 @@ required:
- compatible
- reg
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sm6350-aggre1-noc
then:
properties:
clocks:
items:
- description: aggre UFS PHY AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm6350-aggre2-noc
then:
properties:
clocks:
items:
- description: aggre USB3 PRIM AXI clock
- description: RPMH CC IPA clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm6350-aggre1-noc
- qcom,sm6350-aggre2-noc
then:
required:
- clocks
else:
properties:
clocks: false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm6350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
config_noc: interconnect@1500000 {
compatible = "qcom,sm6350-config-noc";
reg = <0x01500000 0x28000>;
@@ -68,14 +109,16 @@ examples:
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1620000 {
compatible = "qcom,sm6350-system-noc";
reg = <0x01620000 0x17080>;
aggre2_noc: interconnect@1700000 {
compatible = "qcom,sm6350-aggre2-noc";
reg = <0x01700000 0x1f880>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&rpmhcc RPMH_IPA_CLK>;
clk_virt: interconnect-clk-virt {
compatible = "qcom,sm6350-clk-virt";
compute_noc: interconnect-compute-noc {
compatible = "qcom,sm6350-compute-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

3
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@@ -3496,6 +3496,9 @@ usb2: usb@76f8800 {
<&gcc GCC_USB20_MASTER_CLK>;
assigned-clock-rates = <19200000>, <60000000>;
interconnects = <&pnoc MASTER_USB_HS &bimc SLAVE_EBI_CH0>,
<&bimc MASTER_AMPSS_M0 &pnoc SLAVE_USB_HS>;
interconnect-names = "usb-ddr", "apps-usb";
power-domains = <&gcc USB30_GDSC>;
qcom,select-utmi-as-pipe-clk;
status = "disabled";

7
drivers/interconnect/debugfs-client.c
View File

@@ -117,7 +117,12 @@ static int icc_commit_set(void *data, u64 val)
mutex_lock(&debugfs_lock);
if (IS_ERR_OR_NULL(cur_path)) {
if (!cur_path) {
ret = -EINVAL;
goto out;
}
if (IS_ERR(cur_path)) {
ret = PTR_ERR(cur_path);
goto out;
}

9
drivers/interconnect/qcom/Kconfig
View File

@@ -17,6 +17,15 @@ config INTERCONNECT_QCOM_GLYMUR
This is a driver for the Qualcomm Network-on-Chip on glymur-based
platforms.
config INTERCONNECT_QCOM_KAANAPALI
tristate "Qualcomm KAANAPALI interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on kaanapali-based
platforms.
config INTERCONNECT_QCOM_MSM8909
tristate "Qualcomm MSM8909 interconnect driver"
depends on INTERCONNECT_QCOM

2
drivers/interconnect/qcom/Makefile
View File

@@ -5,6 +5,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM) += interconnect_qcom.o
interconnect_qcom-y := icc-common.o
icc-bcm-voter-objs := bcm-voter.o
qnoc-glymur-objs := glymur.o
qnoc-kaanapali-objs := kaanapali.o
qnoc-milos-objs := milos.o
qnoc-msm8909-objs := msm8909.o
qnoc-msm8916-objs := msm8916.o
@@ -48,6 +49,7 @@ icc-smd-rpm-objs := smd-rpm.o icc-rpm.o icc-rpm-clocks.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) += qnoc-glymur.o
obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) += qnoc-kaanapali.o
obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) += qnoc-milos.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o

225
drivers/interconnect/qcom/glymur.c
View File

@@ -457,7 +457,7 @@ static struct qcom_icc_node qup0_core_master = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qup0_core_slave },
.link_nodes = { &qup0_core_slave },
};
static struct qcom_icc_node qup1_core_master = {
@@ -465,7 +465,7 @@ static struct qcom_icc_node qup1_core_master = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qup1_core_slave },
.link_nodes = { &qup1_core_slave },
};
static struct qcom_icc_node qup2_core_master = {
@@ -473,7 +473,7 @@ static struct qcom_icc_node qup2_core_master = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qup2_core_slave },
.link_nodes = { &qup2_core_slave },
};
static struct qcom_icc_node llcc_mc = {
@@ -481,7 +481,7 @@ static struct qcom_icc_node llcc_mc = {
.channels = 12,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &ebi },
.link_nodes = { &ebi },
};
static struct qcom_icc_node qsm_mnoc_cfg = {
@@ -489,7 +489,7 @@ static struct qcom_icc_node qsm_mnoc_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc },
.link_nodes = { &srvc_mnoc },
};
static struct qcom_icc_node qsm_pcie_east_anoc_cfg = {
@@ -497,7 +497,7 @@ static struct qcom_icc_node qsm_pcie_east_anoc_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &srvc_pcie_east_aggre_noc },
.link_nodes = { &srvc_pcie_east_aggre_noc },
};
static struct qcom_icc_node qnm_hscnoc_pcie_east = {
@@ -505,7 +505,7 @@ static struct qcom_icc_node qnm_hscnoc_pcie_east = {
.channels = 1,
.buswidth = 32,
.num_links = 3,
.link_nodes = (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1,
.link_nodes = { &xs_pcie_0, &xs_pcie_1,
&xs_pcie_5 },
};
@@ -514,7 +514,7 @@ static struct qcom_icc_node qsm_cnoc_pcie_east_slave_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qhs_hscnoc_pcie_east_ms_mpu_cfg,
.link_nodes = { &qhs_hscnoc_pcie_east_ms_mpu_cfg,
&srvc_pcie_east },
};
@@ -523,7 +523,7 @@ static struct qcom_icc_node qsm_pcie_west_anoc_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &srvc_pcie_west_aggre_noc },
.link_nodes = { &srvc_pcie_west_aggre_noc },
};
static struct qcom_icc_node qnm_hscnoc_pcie_west = {
@@ -531,7 +531,7 @@ static struct qcom_icc_node qnm_hscnoc_pcie_west = {
.channels = 1,
.buswidth = 32,
.num_links = 5,
.link_nodes = (struct qcom_icc_node *[]) { &xs_pcie_2, &xs_pcie_3a,
.link_nodes = { &xs_pcie_2, &xs_pcie_3a,
&xs_pcie_3b, &xs_pcie_4,
&xs_pcie_6 },
};
@@ -541,7 +541,7 @@ static struct qcom_icc_node qsm_cnoc_pcie_west_slave_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qhs_hscnoc_pcie_west_ms_mpu_cfg,
.link_nodes = { &qhs_hscnoc_pcie_west_ms_mpu_cfg,
&srvc_pcie_west },
};
@@ -550,7 +550,7 @@ static struct qcom_icc_node qss_cnoc_pcie_slave_east_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qsm_cnoc_pcie_east_slave_cfg },
.link_nodes = { &qsm_cnoc_pcie_east_slave_cfg },
};
static struct qcom_icc_node qss_cnoc_pcie_slave_west_cfg = {
@@ -558,7 +558,7 @@ static struct qcom_icc_node qss_cnoc_pcie_slave_west_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qsm_cnoc_pcie_west_slave_cfg },
.link_nodes = { &qsm_cnoc_pcie_west_slave_cfg },
};
static struct qcom_icc_node qss_mnoc_cfg = {
@@ -566,7 +566,7 @@ static struct qcom_icc_node qss_mnoc_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qsm_mnoc_cfg },
.link_nodes = { &qsm_mnoc_cfg },
};
static struct qcom_icc_node qss_pcie_east_anoc_cfg = {
@@ -574,7 +574,7 @@ static struct qcom_icc_node qss_pcie_east_anoc_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qsm_pcie_east_anoc_cfg },
.link_nodes = { &qsm_pcie_east_anoc_cfg },
};
static struct qcom_icc_node qss_pcie_west_anoc_cfg = {
@@ -582,7 +582,7 @@ static struct qcom_icc_node qss_pcie_west_anoc_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qsm_pcie_west_anoc_cfg },
.link_nodes = { &qsm_pcie_west_anoc_cfg },
};
static struct qcom_icc_node qns_llcc = {
@@ -590,7 +590,7 @@ static struct qcom_icc_node qns_llcc = {
.channels = 12,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &llcc_mc },
.link_nodes = { &llcc_mc },
};
static struct qcom_icc_node qns_pcie_east = {
@@ -598,7 +598,7 @@ static struct qcom_icc_node qns_pcie_east = {
.channels = 1,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_hscnoc_pcie_east },
.link_nodes = { &qnm_hscnoc_pcie_east },
};
static struct qcom_icc_node qns_pcie_west = {
@@ -606,7 +606,7 @@ static struct qcom_icc_node qns_pcie_west = {
.channels = 1,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_hscnoc_pcie_west },
.link_nodes = { &qnm_hscnoc_pcie_west },
};
static struct qcom_icc_node qsm_cfg = {
@@ -614,7 +614,7 @@ static struct qcom_icc_node qsm_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 51,
.link_nodes = (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1,
.link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
&qhs_ahb2phy2, &qhs_ahb2phy3,
&qhs_av1_enc_cfg, &qhs_camera_cfg,
&qhs_clk_ctl, &qhs_crypto0_cfg,
@@ -654,7 +654,7 @@ static struct qcom_icc_node xm_gic = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_llcc },
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_node qss_cfg = {
@@ -662,7 +662,7 @@ static struct qcom_icc_node qss_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qsm_cfg },
.link_nodes = { &qsm_cfg },
};
static struct qcom_icc_node qnm_hscnoc_cnoc = {
@@ -670,7 +670,7 @@ static struct qcom_icc_node qnm_hscnoc_cnoc = {
.channels = 1,
.buswidth = 16,
.num_links = 8,
.link_nodes = (struct qcom_icc_node *[]) { &qhs_aoss, &qhs_ipc_router,
.link_nodes = { &qhs_aoss, &qhs_ipc_router,
&qhs_soccp, &qhs_tme_cfg,
&qns_apss, &qss_cfg,
&qxs_boot_imem, &qxs_imem },
@@ -681,7 +681,7 @@ static struct qcom_icc_node qns_hscnoc_cnoc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_hscnoc_cnoc },
.link_nodes = { &qnm_hscnoc_cnoc },
};
static struct qcom_icc_node alm_gpu_tcu = {
@@ -696,7 +696,7 @@ static struct qcom_icc_node alm_gpu_tcu = {
.prio_fwd_disable = 1,
},
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc },
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc },
};
static struct qcom_icc_node alm_pcie_qtc = {
@@ -711,7 +711,7 @@ static struct qcom_icc_node alm_pcie_qtc = {
.prio_fwd_disable = 1,
},
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc },
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc },
};
static struct qcom_icc_node alm_sys_tcu = {
@@ -726,7 +726,7 @@ static struct qcom_icc_node alm_sys_tcu = {
.prio_fwd_disable = 1,
},
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc },
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc },
};
static struct qcom_icc_node chm_apps = {
@@ -734,7 +734,7 @@ static struct qcom_icc_node chm_apps = {
.channels = 6,
.buswidth = 32,
.num_links = 4,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc,
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
&qns_pcie_east, &qns_pcie_west },
};
@@ -750,7 +750,7 @@ static struct qcom_icc_node qnm_aggre_noc_east = {
.prio_fwd_disable = 1,
},
.num_links = 4,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc,
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
&qns_pcie_east, &qns_pcie_west },
};
@@ -766,7 +766,7 @@ static struct qcom_icc_node qnm_gpu = {
.prio_fwd_disable = 1,
},
.num_links = 4,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc,
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
&qns_pcie_east, &qns_pcie_west },
};
@@ -782,7 +782,7 @@ static struct qcom_icc_node qnm_lpass = {
.prio_fwd_disable = 0,
},
.num_links = 4,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc,
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
&qns_pcie_east, &qns_pcie_west },
};
@@ -798,7 +798,7 @@ static struct qcom_icc_node qnm_mnoc_hf = {
.prio_fwd_disable = 0,
},
.num_links = 4,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc,
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
&qns_pcie_east, &qns_pcie_west },
};
@@ -814,7 +814,7 @@ static struct qcom_icc_node qnm_mnoc_sf = {
.prio_fwd_disable = 0,
},
.num_links = 4,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc,
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
&qns_pcie_east, &qns_pcie_west },
};
@@ -830,7 +830,7 @@ static struct qcom_icc_node qnm_nsp_noc = {
.prio_fwd_disable = 1,
},
.num_links = 4,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc,
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
&qns_pcie_east, &qns_pcie_west },
};
@@ -846,7 +846,7 @@ static struct qcom_icc_node qnm_pcie_east = {
.prio_fwd_disable = 1,
},
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc },
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_pcie_west = {
@@ -861,7 +861,7 @@ static struct qcom_icc_node qnm_pcie_west = {
.prio_fwd_disable = 1,
},
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc },
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_snoc_sf = {
@@ -876,7 +876,7 @@ static struct qcom_icc_node qnm_snoc_sf = {
.prio_fwd_disable = 1,
},
.num_links = 4,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc,
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
&qns_pcie_east, &qns_pcie_west },
};
@@ -885,7 +885,7 @@ static struct qcom_icc_node qxm_wlan_q6 = {
.channels = 1,
.buswidth = 8,
.num_links = 4,
.link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc,
.link_nodes = { &qns_hscnoc_cnoc, &qns_llcc,
&qns_pcie_east, &qns_pcie_west },
};
@@ -894,7 +894,7 @@ static struct qcom_icc_node qns_a4noc_hscnoc = {
.channels = 1,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre_noc_east },
.link_nodes = { &qnm_aggre_noc_east },
};
static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
@@ -902,7 +902,7 @@ static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass },
.link_nodes = { &qnm_lpass },
};
static struct qcom_icc_node qns_mem_noc_hf = {
@@ -910,7 +910,7 @@ static struct qcom_icc_node qns_mem_noc_hf = {
.channels = 2,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf },
.link_nodes = { &qnm_mnoc_hf },
};
static struct qcom_icc_node qns_mem_noc_sf = {
@@ -918,7 +918,7 @@ static struct qcom_icc_node qns_mem_noc_sf = {
.channels = 2,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf },
.link_nodes = { &qnm_mnoc_sf },
};
static struct qcom_icc_node qns_nsp_hscnoc = {
@@ -926,7 +926,7 @@ static struct qcom_icc_node qns_nsp_hscnoc = {
.channels = 4,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_nsp_noc },
.link_nodes = { &qnm_nsp_noc },
};
static struct qcom_icc_node qns_pcie_east_mem_noc = {
@@ -934,7 +934,7 @@ static struct qcom_icc_node qns_pcie_east_mem_noc = {
.channels = 1,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_pcie_east },
.link_nodes = { &qnm_pcie_east },
};
static struct qcom_icc_node qns_pcie_west_mem_noc = {
@@ -942,7 +942,7 @@ static struct qcom_icc_node qns_pcie_west_mem_noc = {
.channels = 1,
.buswidth = 64,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_pcie_west },
.link_nodes = { &qnm_pcie_west },
};
static struct qcom_icc_node qns_gemnoc_sf = {
@@ -950,7 +950,7 @@ static struct qcom_icc_node qns_gemnoc_sf = {
.channels = 1,
.buswidth = 64,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_sf },
.link_nodes = { &qnm_snoc_sf },
};
static struct qcom_icc_node xm_usb3_0 = {
@@ -965,7 +965,7 @@ static struct qcom_icc_node xm_usb3_0 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc },
.link_nodes = { &qns_a4noc_hscnoc },
};
static struct qcom_icc_node xm_usb3_1 = {
@@ -980,7 +980,7 @@ static struct qcom_icc_node xm_usb3_1 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc },
.link_nodes = { &qns_a4noc_hscnoc },
};
static struct qcom_icc_node xm_usb4_0 = {
@@ -995,7 +995,7 @@ static struct qcom_icc_node xm_usb4_0 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc },
.link_nodes = { &qns_a4noc_hscnoc },
};
static struct qcom_icc_node xm_usb4_1 = {
@@ -1010,7 +1010,7 @@ static struct qcom_icc_node xm_usb4_1 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc },
.link_nodes = { &qns_a4noc_hscnoc },
};
static struct qcom_icc_node qnm_lpiaon_noc = {
@@ -1018,7 +1018,7 @@ static struct qcom_icc_node qnm_lpiaon_noc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_lpass_ag_noc_gemnoc },
.link_nodes = { &qns_lpass_ag_noc_gemnoc },
};
static struct qcom_icc_node qnm_av1_enc = {
@@ -1033,7 +1033,7 @@ static struct qcom_icc_node qnm_av1_enc = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_camnoc_hf = {
@@ -1048,7 +1048,7 @@ static struct qcom_icc_node qnm_camnoc_hf = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
.link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_node qnm_camnoc_icp = {
@@ -1063,7 +1063,7 @@ static struct qcom_icc_node qnm_camnoc_icp = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_camnoc_sf = {
@@ -1078,7 +1078,7 @@ static struct qcom_icc_node qnm_camnoc_sf = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_eva = {
@@ -1093,7 +1093,7 @@ static struct qcom_icc_node qnm_eva = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_mdp = {
@@ -1108,7 +1108,7 @@ static struct qcom_icc_node qnm_mdp = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
.link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_node qnm_vapss_hcp = {
@@ -1116,7 +1116,7 @@ static struct qcom_icc_node qnm_vapss_hcp = {
.channels = 1,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_video = {
@@ -1131,7 +1131,7 @@ static struct qcom_icc_node qnm_video = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_video_cv_cpu = {
@@ -1146,7 +1146,7 @@ static struct qcom_icc_node qnm_video_cv_cpu = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_video_v_cpu = {
@@ -1161,7 +1161,7 @@ static struct qcom_icc_node qnm_video_v_cpu = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_nsp = {
@@ -1169,7 +1169,7 @@ static struct qcom_icc_node qnm_nsp = {
.channels = 4,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_nsp_hscnoc },
.link_nodes = { &qns_nsp_hscnoc },
};
static struct qcom_icc_node xm_pcie_0 = {
@@ -1184,7 +1184,7 @@ static struct qcom_icc_node xm_pcie_0 = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc },
.link_nodes = { &qns_pcie_east_mem_noc },
};
static struct qcom_icc_node xm_pcie_1 = {
@@ -1199,7 +1199,7 @@ static struct qcom_icc_node xm_pcie_1 = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc },
.link_nodes = { &qns_pcie_east_mem_noc },
};
static struct qcom_icc_node xm_pcie_5 = {
@@ -1214,7 +1214,7 @@ static struct qcom_icc_node xm_pcie_5 = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc },
.link_nodes = { &qns_pcie_east_mem_noc },
};
static struct qcom_icc_node xm_pcie_2 = {
@@ -1229,7 +1229,7 @@ static struct qcom_icc_node xm_pcie_2 = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc },
.link_nodes = { &qns_pcie_west_mem_noc },
};
static struct qcom_icc_node xm_pcie_3a = {
@@ -1244,7 +1244,7 @@ static struct qcom_icc_node xm_pcie_3a = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc },
.link_nodes = { &qns_pcie_west_mem_noc },
};
static struct qcom_icc_node xm_pcie_3b = {
@@ -1259,7 +1259,7 @@ static struct qcom_icc_node xm_pcie_3b = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc },
.link_nodes = { &qns_pcie_west_mem_noc },
};
static struct qcom_icc_node xm_pcie_4 = {
@@ -1274,7 +1274,7 @@ static struct qcom_icc_node xm_pcie_4 = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc },
.link_nodes = { &qns_pcie_west_mem_noc },
};
static struct qcom_icc_node xm_pcie_6 = {
@@ -1289,7 +1289,7 @@ static struct qcom_icc_node xm_pcie_6 = {
.prio_fwd_disable = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc },
.link_nodes = { &qns_pcie_west_mem_noc },
};
static struct qcom_icc_node qnm_aggre1_noc = {
@@ -1297,7 +1297,7 @@ static struct qcom_icc_node qnm_aggre1_noc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qnm_aggre2_noc = {
@@ -1305,7 +1305,7 @@ static struct qcom_icc_node qnm_aggre2_noc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qnm_aggre3_noc = {
@@ -1313,7 +1313,7 @@ static struct qcom_icc_node qnm_aggre3_noc = {
.channels = 1,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qnm_nsi_noc = {
@@ -1328,7 +1328,7 @@ static struct qcom_icc_node qnm_nsi_noc = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qnm_oobmss = {
@@ -1343,7 +1343,7 @@ static struct qcom_icc_node qnm_oobmss = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qns_a1noc_snoc = {
@@ -1351,7 +1351,7 @@ static struct qcom_icc_node qns_a1noc_snoc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre1_noc },
.link_nodes = { &qnm_aggre1_noc },
};
static struct qcom_icc_node qns_a2noc_snoc = {
@@ -1359,7 +1359,7 @@ static struct qcom_icc_node qns_a2noc_snoc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre2_noc },
.link_nodes = { &qnm_aggre2_noc },
};
static struct qcom_icc_node qns_a3noc_snoc = {
@@ -1367,7 +1367,7 @@ static struct qcom_icc_node qns_a3noc_snoc = {
.channels = 1,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre3_noc },
.link_nodes = { &qnm_aggre3_noc },
};
static struct qcom_icc_node qns_lpass_aggnoc = {
@@ -1375,7 +1375,7 @@ static struct qcom_icc_node qns_lpass_aggnoc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_lpiaon_noc },
.link_nodes = { &qnm_lpiaon_noc },
};
static struct qcom_icc_node qns_system_noc = {
@@ -1383,7 +1383,7 @@ static struct qcom_icc_node qns_system_noc = {
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_nsi_noc },
.link_nodes = { &qnm_nsi_noc },
};
static struct qcom_icc_node qns_oobmss_snoc = {
@@ -1391,7 +1391,7 @@ static struct qcom_icc_node qns_oobmss_snoc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_oobmss },
.link_nodes = { &qnm_oobmss },
};
static struct qcom_icc_node qxm_crypto = {
@@ -1406,7 +1406,7 @@ static struct qcom_icc_node qxm_crypto = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node qxm_soccp = {
@@ -1421,7 +1421,7 @@ static struct qcom_icc_node qxm_soccp = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_qdss_etr_0 = {
@@ -1436,7 +1436,7 @@ static struct qcom_icc_node xm_qdss_etr_0 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_qdss_etr_1 = {
@@ -1451,7 +1451,7 @@ static struct qcom_icc_node xm_qdss_etr_1 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_ufs_mem = {
@@ -1466,7 +1466,7 @@ static struct qcom_icc_node xm_ufs_mem = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node xm_usb3_2 = {
@@ -1481,7 +1481,7 @@ static struct qcom_icc_node xm_usb3_2 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node xm_usb4_2 = {
@@ -1496,7 +1496,7 @@ static struct qcom_icc_node xm_usb4_2 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node qhm_qspi = {
@@ -1511,7 +1511,7 @@ static struct qcom_icc_node qhm_qspi = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc },
.link_nodes = { &qns_a3noc_snoc },
};
static struct qcom_icc_node qhm_qup0 = {
@@ -1526,7 +1526,7 @@ static struct qcom_icc_node qhm_qup0 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc },
.link_nodes = { &qns_a3noc_snoc },
};
static struct qcom_icc_node qhm_qup1 = {
@@ -1541,7 +1541,7 @@ static struct qcom_icc_node qhm_qup1 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc },
.link_nodes = { &qns_a3noc_snoc },
};
static struct qcom_icc_node qhm_qup2 = {
@@ -1556,7 +1556,7 @@ static struct qcom_icc_node qhm_qup2 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc },
.link_nodes = { &qns_a3noc_snoc },
};
static struct qcom_icc_node qxm_sp = {
@@ -1564,7 +1564,7 @@ static struct qcom_icc_node qxm_sp = {
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc },
.link_nodes = { &qns_a3noc_snoc },
};
static struct qcom_icc_node xm_sdc2 = {
@@ -1579,7 +1579,7 @@ static struct qcom_icc_node xm_sdc2 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc },
.link_nodes = { &qns_a3noc_snoc },
};
static struct qcom_icc_node xm_sdc4 = {
@@ -1594,7 +1594,7 @@ static struct qcom_icc_node xm_sdc4 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc },
.link_nodes = { &qns_a3noc_snoc },
};
static struct qcom_icc_node xm_usb2_0 = {
@@ -1609,7 +1609,7 @@ static struct qcom_icc_node xm_usb2_0 = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc },
.link_nodes = { &qns_a3noc_snoc },
};
static struct qcom_icc_node xm_usb3_mp = {
@@ -1624,7 +1624,7 @@ static struct qcom_icc_node xm_usb3_mp = {
.prio_fwd_disable = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc },
.link_nodes = { &qns_a3noc_snoc },
};
static struct qcom_icc_node qnm_lpass_lpinoc = {
@@ -1632,7 +1632,7 @@ static struct qcom_icc_node qnm_lpass_lpinoc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_lpass_aggnoc },
.link_nodes = { &qns_lpass_aggnoc },
};
static struct qcom_icc_node xm_cpucp = {
@@ -1640,7 +1640,7 @@ static struct qcom_icc_node xm_cpucp = {
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_system_noc, &srvc_nsinoc },
.link_nodes = { &qns_system_noc, &srvc_nsinoc },
};
static struct qcom_icc_node xm_mem_sp = {
@@ -1648,7 +1648,7 @@ static struct qcom_icc_node xm_mem_sp = {
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_oobmss_snoc },
.link_nodes = { &qns_oobmss_snoc },
};
static struct qcom_icc_node qns_lpi_aon_noc = {
@@ -1656,7 +1656,7 @@ static struct qcom_icc_node qns_lpi_aon_noc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass_lpinoc },
.link_nodes = { &qnm_lpass_lpinoc },
};
static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = {
@@ -1664,7 +1664,7 @@ static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_lpi_aon_noc },
.link_nodes = { &qns_lpi_aon_noc },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1878,7 +1878,6 @@ static const struct qcom_icc_desc glymur_aggre1_noc = {
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
@@ -1900,7 +1899,6 @@ static const struct qcom_icc_desc glymur_aggre2_noc = {
.config = &glymur_aggre2_noc_regmap_config,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.alloc_dyn_id = true,
.qos_requires_clocks = true,
};
@@ -1929,7 +1927,6 @@ static const struct qcom_icc_desc glymur_aggre3_noc = {
.config = &glymur_aggre3_noc_regmap_config,
.nodes = aggre3_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre3_noc_nodes),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const aggre4_noc_bcms[] = {
@@ -1958,7 +1955,6 @@ static const struct qcom_icc_desc glymur_aggre4_noc = {
.num_nodes = ARRAY_SIZE(aggre4_noc_nodes),
.bcms = aggre4_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre4_noc_bcms),
.alloc_dyn_id = true,
.qos_requires_clocks = true,
};
@@ -1982,7 +1978,6 @@ static const struct qcom_icc_desc glymur_clk_virt = {
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = {
@@ -2059,7 +2054,6 @@ static const struct qcom_icc_desc glymur_cnoc_cfg = {
.num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
.bcms = cnoc_cfg_bcms,
.num_bcms = ARRAY_SIZE(cnoc_cfg_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
@@ -2092,7 +2086,6 @@ static const struct qcom_icc_desc glymur_cnoc_main = {
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
.num_bcms = ARRAY_SIZE(cnoc_main_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const hscnoc_bcms[] = {
@@ -2136,7 +2129,6 @@ static const struct qcom_icc_desc glymur_hscnoc = {
.num_nodes = ARRAY_SIZE(hscnoc_nodes),
.bcms = hscnoc_bcms,
.num_bcms = ARRAY_SIZE(hscnoc_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
@@ -2156,7 +2148,6 @@ static const struct qcom_icc_desc glymur_lpass_ag_noc = {
.config = &glymur_lpass_ag_noc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
@@ -2182,7 +2173,6 @@ static const struct qcom_icc_desc glymur_lpass_lpiaon_noc = {
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
.bcms = lpass_lpiaon_noc_bcms,
.num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
@@ -2202,7 +2192,6 @@ static const struct qcom_icc_desc glymur_lpass_lpicx_noc = {
.config = &glymur_lpass_lpicx_noc_regmap_config,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
@@ -2220,7 +2209,6 @@ static const struct qcom_icc_desc glymur_mc_virt = {
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
@@ -2259,7 +2247,6 @@ static const struct qcom_icc_desc glymur_mmss_noc = {
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_node * const nsinoc_nodes[] = {
@@ -2280,7 +2267,6 @@ static const struct qcom_icc_desc glymur_nsinoc = {
.config = &glymur_nsinoc_regmap_config,
.nodes = nsinoc_nodes,
.num_nodes = ARRAY_SIZE(nsinoc_nodes),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
@@ -2306,7 +2292,6 @@ static const struct qcom_icc_desc glymur_nsp_noc = {
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_node * const oobm_ss_noc_nodes[] = {
@@ -2326,7 +2311,6 @@ static const struct qcom_icc_desc glymur_oobm_ss_noc = {
.config = &glymur_oobm_ss_noc_regmap_config,
.nodes = oobm_ss_noc_nodes,
.num_nodes = ARRAY_SIZE(oobm_ss_noc_nodes),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const pcie_east_anoc_bcms[] = {
@@ -2356,7 +2340,6 @@ static const struct qcom_icc_desc glymur_pcie_east_anoc = {
.num_nodes = ARRAY_SIZE(pcie_east_anoc_nodes),
.bcms = pcie_east_anoc_bcms,
.num_bcms = ARRAY_SIZE(pcie_east_anoc_bcms),
.alloc_dyn_id = true,
.qos_requires_clocks = true,
};
@@ -2388,7 +2371,6 @@ static const struct qcom_icc_desc glymur_pcie_east_slv_noc = {
.num_nodes = ARRAY_SIZE(pcie_east_slv_noc_nodes),
.bcms = pcie_east_slv_noc_bcms,
.num_bcms = ARRAY_SIZE(pcie_east_slv_noc_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const pcie_west_anoc_bcms[] = {
@@ -2420,7 +2402,6 @@ static const struct qcom_icc_desc glymur_pcie_west_anoc = {
.num_nodes = ARRAY_SIZE(pcie_west_anoc_nodes),
.bcms = pcie_west_anoc_bcms,
.num_bcms = ARRAY_SIZE(pcie_west_anoc_bcms),
.alloc_dyn_id = true,
.qos_requires_clocks = true,
};
@@ -2454,7 +2435,6 @@ static const struct qcom_icc_desc glymur_pcie_west_slv_noc = {
.num_nodes = ARRAY_SIZE(pcie_west_slv_noc_nodes),
.bcms = pcie_west_slv_noc_bcms,
.num_bcms = ARRAY_SIZE(pcie_west_slv_noc_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const system_noc_bcms[] = {
@@ -2488,7 +2468,6 @@ static const struct qcom_icc_desc glymur_system_noc = {
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
.alloc_dyn_id = true,
};
static const struct of_device_id qnoc_of_match[] = {

37
drivers/interconnect/qcom/icc-rpmh.c
View File

@@ -280,14 +280,10 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
if (!qn)
continue;
if (desc->alloc_dyn_id) {
if (!qn->node)
qn->node = icc_node_create_dyn();
node = qn->node;
} else {
node = icc_node_create(qn->id);
}
if (!qn->node)
qn->node = icc_node_create_dyn();
node = qn->node;
if (IS_ERR(node)) {
ret = PTR_ERR(node);
goto err_remove_nodes;
@@ -302,12 +298,8 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
node->data = qn;
icc_node_add(node, provider);
for (j = 0; j < qn->num_links; j++) {
if (desc->alloc_dyn_id)
icc_link_nodes(node, &qn->link_nodes[j]->node);
else
icc_link_create(node, qn->links[j]);
}
for (j = 0; j < qn->num_links; j++)
icc_link_nodes(node, &qn->link_nodes[j]->node);
data->nodes[i] = node;
}
@@ -316,14 +308,19 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
struct resource *res;
void __iomem *base;
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
goto skip_qos_config;
/* Try parent's regmap first */
qp->regmap = dev_get_regmap(dev->parent, NULL);
if (!qp->regmap) {
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
goto skip_qos_config;
qp->regmap = devm_regmap_init_mmio(dev, base, desc->config);
if (IS_ERR(qp->regmap)) {
dev_info(dev, "Skipping QoS, regmap failed; %ld\n", PTR_ERR(qp->regmap));
goto skip_qos_config;
qp->regmap = devm_regmap_init_mmio(dev, base, desc->config);
if (IS_ERR(qp->regmap)) {
dev_info(dev, "Skipping QoS, regmap failed; %ld\n",
PTR_ERR(qp->regmap));
goto skip_qos_config;
}
}
qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks);

7
drivers/interconnect/qcom/icc-rpmh.h
View File

@@ -81,8 +81,6 @@ struct qcom_icc_qosbox {
/**
* struct qcom_icc_node - Qualcomm specific interconnect nodes
* @name: the node name used in debugfs
* @links: an array of nodes where we can go next while traversing
* @id: a unique node identifier
* @link_nodes: links associated with this node
* @node: icc_node associated with this node
* @num_links: the total number of @links
@@ -96,9 +94,6 @@ struct qcom_icc_qosbox {
*/
struct qcom_icc_node {
const char *name;
u16 links[MAX_LINKS];
u16 id;
struct qcom_icc_node **link_nodes;
struct icc_node *node;
u16 num_links;
u16 channels;
@@ -108,6 +103,7 @@ struct qcom_icc_node {
struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE];
size_t num_bcms;
const struct qcom_icc_qosbox *qosbox;
struct qcom_icc_node *link_nodes[];
};
/**
@@ -158,7 +154,6 @@ struct qcom_icc_desc {
struct qcom_icc_bcm * const *bcms;
size_t num_bcms;
bool qos_requires_clocks;
bool alloc_dyn_id;
};
int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,

1855
drivers/interconnect/qcom/kaanapali.c Normal file
View File

File diff suppressed because it is too large Load Diff

142
drivers/interconnect/qcom/milos.c
View File

@@ -151,7 +151,7 @@ static struct qcom_icc_node qhm_qup1 = {
.buswidth = 4,
.qosbox = &qhm_qup1_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_ufs_mem_qos = {
@@ -168,7 +168,7 @@ static struct qcom_icc_node xm_ufs_mem = {
.buswidth = 8,
.qosbox = &xm_ufs_mem_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_usb3_0_qos = {
@@ -185,7 +185,7 @@ static struct qcom_icc_node xm_usb3_0 = {
.buswidth = 8,
.qosbox = &xm_usb3_0_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
@@ -202,7 +202,7 @@ static struct qcom_icc_node qhm_qdss_bam = {
.buswidth = 4,
.qosbox = &qhm_qdss_bam_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qhm_qspi_qos = {
@@ -219,7 +219,7 @@ static struct qcom_icc_node qhm_qspi = {
.buswidth = 4,
.qosbox = &qhm_qspi_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qhm_qup0_qos = {
@@ -236,7 +236,7 @@ static struct qcom_icc_node qhm_qup0 = {
.buswidth = 4,
.qosbox = &qhm_qup0_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_crypto_qos = {
@@ -253,7 +253,7 @@ static struct qcom_icc_node qxm_crypto = {
.buswidth = 8,
.qosbox = &qxm_crypto_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_ipa_qos = {
@@ -270,7 +270,7 @@ static struct qcom_icc_node qxm_ipa = {
.buswidth = 8,
.qosbox = &qxm_ipa_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
@@ -287,7 +287,7 @@ static struct qcom_icc_node xm_qdss_etr_0 = {
.buswidth = 8,
.qosbox = &xm_qdss_etr_0_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
@@ -304,7 +304,7 @@ static struct qcom_icc_node xm_qdss_etr_1 = {
.buswidth = 8,
.qosbox = &xm_qdss_etr_1_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_sdc1_qos = {
@@ -321,7 +321,7 @@ static struct qcom_icc_node xm_sdc1 = {
.buswidth = 8,
.qosbox = &xm_sdc1_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_sdc2_qos = {
@@ -338,7 +338,7 @@ static struct qcom_icc_node xm_sdc2 = {
.buswidth = 8,
.qosbox = &xm_sdc2_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node qup0_core_master = {
@@ -346,7 +346,7 @@ static struct qcom_icc_node qup0_core_master = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qup0_core_slave },
.link_nodes = { &qup0_core_slave },
};
static struct qcom_icc_node qup1_core_master = {
@@ -354,7 +354,7 @@ static struct qcom_icc_node qup1_core_master = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qup1_core_slave },
.link_nodes = { &qup1_core_slave },
};
static struct qcom_icc_node qsm_cfg = {
@@ -362,7 +362,7 @@ static struct qcom_icc_node qsm_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 35,
.link_nodes = (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1,
.link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
&qhs_camera_cfg, &qhs_clk_ctl,
&qhs_cpr_cx, &qhs_cpr_mxa,
&qhs_crypto0_cfg, &qhs_cx_rdpm,
@@ -387,7 +387,7 @@ static struct qcom_icc_node qnm_gemnoc_cnoc = {
.channels = 1,
.buswidth = 16,
.num_links = 14,
.link_nodes = (struct qcom_icc_node *[]) { &qhs_aoss, &qhs_display_cfg,
.link_nodes = { &qhs_aoss, &qhs_display_cfg,
&qhs_ipa, &qhs_ipc_router,
&qhs_pcie0_cfg, &qhs_pcie1_cfg,
&qhs_prng, &qhs_tme_cfg,
@@ -401,7 +401,7 @@ static struct qcom_icc_node qnm_gemnoc_pcie = {
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1 },
.link_nodes = { &xs_pcie_0, &xs_pcie_1 },
};
static struct qcom_icc_qosbox alm_gpu_tcu_qos = {
@@ -418,7 +418,7 @@ static struct qcom_icc_node alm_gpu_tcu = {
.buswidth = 8,
.qosbox = &alm_gpu_tcu_qos,
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox alm_sys_tcu_qos = {
@@ -435,7 +435,7 @@ static struct qcom_icc_node alm_sys_tcu = {
.buswidth = 8,
.qosbox = &alm_sys_tcu_qos,
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node chm_apps = {
@@ -443,7 +443,7 @@ static struct qcom_icc_node chm_apps = {
.channels = 3,
.buswidth = 32,
.num_links = 3,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
&qns_pcie },
};
@@ -461,7 +461,7 @@ static struct qcom_icc_node qnm_gpu = {
.buswidth = 32,
.qosbox = &qnm_gpu_qos,
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
@@ -478,7 +478,7 @@ static struct qcom_icc_node qnm_lpass_gemnoc = {
.buswidth = 16,
.qosbox = &qnm_lpass_gemnoc_qos,
.num_links = 3,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
&qns_pcie },
};
@@ -487,7 +487,7 @@ static struct qcom_icc_node qnm_mdsp = {
.channels = 1,
.buswidth = 16,
.num_links = 3,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
&qns_pcie },
};
@@ -505,7 +505,7 @@ static struct qcom_icc_node qnm_mnoc_hf = {
.buswidth = 32,
.qosbox = &qnm_mnoc_hf_qos,
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
@@ -522,7 +522,7 @@ static struct qcom_icc_node qnm_mnoc_sf = {
.buswidth = 32,
.qosbox = &qnm_mnoc_sf_qos,
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
@@ -539,7 +539,7 @@ static struct qcom_icc_node qnm_nsp_gemnoc = {
.buswidth = 32,
.qosbox = &qnm_nsp_gemnoc_qos,
.num_links = 3,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
&qns_pcie },
};
@@ -557,7 +557,7 @@ static struct qcom_icc_node qnm_pcie = {
.buswidth = 8,
.qosbox = &qnm_pcie_qos,
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_snoc_gc_qos = {
@@ -574,7 +574,7 @@ static struct qcom_icc_node qnm_snoc_gc = {
.buswidth = 8,
.qosbox = &qnm_snoc_gc_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_llcc },
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
@@ -591,7 +591,7 @@ static struct qcom_icc_node qnm_snoc_sf = {
.buswidth = 16,
.qosbox = &qnm_snoc_sf_qos,
.num_links = 3,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
&qns_pcie },
};
@@ -600,7 +600,7 @@ static struct qcom_icc_node qxm_wlan_q6 = {
.channels = 1,
.buswidth = 8,
.num_links = 3,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
&qns_pcie },
};
@@ -609,7 +609,7 @@ static struct qcom_icc_node qxm_lpass_dsp = {
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_lpass_ag_noc_gemnoc },
.link_nodes = { &qns_lpass_ag_noc_gemnoc },
};
static struct qcom_icc_node llcc_mc = {
@@ -617,7 +617,7 @@ static struct qcom_icc_node llcc_mc = {
.channels = 2,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &ebi },
.link_nodes = { &ebi },
};
static struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
@@ -634,7 +634,7 @@ static struct qcom_icc_node qnm_camnoc_hf = {
.buswidth = 32,
.qosbox = &qnm_camnoc_hf_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
.link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
@@ -651,7 +651,7 @@ static struct qcom_icc_node qnm_camnoc_icp = {
.buswidth = 8,
.qosbox = &qnm_camnoc_icp_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
@@ -668,7 +668,7 @@ static struct qcom_icc_node qnm_camnoc_sf = {
.buswidth = 32,
.qosbox = &qnm_camnoc_sf_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_mdp_qos = {
@@ -685,7 +685,7 @@ static struct qcom_icc_node qnm_mdp = {
.buswidth = 32,
.qosbox = &qnm_mdp_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
.link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_qosbox qnm_video_qos = {
@@ -702,7 +702,7 @@ static struct qcom_icc_node qnm_video = {
.buswidth = 32,
.qosbox = &qnm_video_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_node qsm_hf_mnoc_cfg = {
@@ -710,7 +710,7 @@ static struct qcom_icc_node qsm_hf_mnoc_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc_hf },
.link_nodes = { &srvc_mnoc_hf },
};
static struct qcom_icc_node qsm_sf_mnoc_cfg = {
@@ -718,7 +718,7 @@ static struct qcom_icc_node qsm_sf_mnoc_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc_sf },
.link_nodes = { &srvc_mnoc_sf },
};
static struct qcom_icc_node qxm_nsp = {
@@ -726,7 +726,7 @@ static struct qcom_icc_node qxm_nsp = {
.channels = 2,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_nsp_gemnoc },
.link_nodes = { &qns_nsp_gemnoc },
};
static struct qcom_icc_node qsm_pcie_anoc_cfg = {
@@ -734,7 +734,7 @@ static struct qcom_icc_node qsm_pcie_anoc_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &srvc_pcie_aggre_noc },
.link_nodes = { &srvc_pcie_aggre_noc },
};
static struct qcom_icc_qosbox xm_pcie3_0_qos = {
@@ -751,7 +751,7 @@ static struct qcom_icc_node xm_pcie3_0 = {
.buswidth = 8,
.qosbox = &xm_pcie3_0_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc },
.link_nodes = { &qns_pcie_mem_noc },
};
static struct qcom_icc_qosbox xm_pcie3_1_qos = {
@@ -768,7 +768,7 @@ static struct qcom_icc_node xm_pcie3_1 = {
.buswidth = 8,
.qosbox = &xm_pcie3_1_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc },
.link_nodes = { &qns_pcie_mem_noc },
};
static struct qcom_icc_node qnm_aggre1_noc = {
@@ -776,7 +776,7 @@ static struct qcom_icc_node qnm_aggre1_noc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qnm_aggre2_noc = {
@@ -784,7 +784,7 @@ static struct qcom_icc_node qnm_aggre2_noc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_qosbox qnm_apss_noc_qos = {
@@ -801,7 +801,7 @@ static struct qcom_icc_node qnm_apss_noc = {
.buswidth = 4,
.qosbox = &qnm_apss_noc_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_qosbox qnm_cnoc_data_qos = {
@@ -818,7 +818,7 @@ static struct qcom_icc_node qnm_cnoc_data = {
.buswidth = 8,
.qosbox = &qnm_cnoc_data_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_qosbox qxm_pimem_qos = {
@@ -835,7 +835,7 @@ static struct qcom_icc_node qxm_pimem = {
.buswidth = 8,
.qosbox = &qxm_pimem_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc },
.link_nodes = { &qns_gemnoc_gc },
};
static struct qcom_icc_qosbox xm_gic_qos = {
@@ -852,7 +852,7 @@ static struct qcom_icc_node xm_gic = {
.buswidth = 8,
.qosbox = &xm_gic_qos,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc },
.link_nodes = { &qns_gemnoc_gc },
};
static struct qcom_icc_node qns_a1noc_snoc = {
@@ -860,7 +860,7 @@ static struct qcom_icc_node qns_a1noc_snoc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre1_noc },
.link_nodes = { &qnm_aggre1_noc },
};
static struct qcom_icc_node qns_a2noc_snoc = {
@@ -868,7 +868,7 @@ static struct qcom_icc_node qns_a2noc_snoc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre2_noc },
.link_nodes = { &qnm_aggre2_noc },
};
static struct qcom_icc_node qup0_core_slave = {
@@ -1079,7 +1079,7 @@ static struct qcom_icc_node qss_mnoc_hf_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qsm_hf_mnoc_cfg },
.link_nodes = { &qsm_hf_mnoc_cfg },
};
static struct qcom_icc_node qss_mnoc_sf_cfg = {
@@ -1087,7 +1087,7 @@ static struct qcom_icc_node qss_mnoc_sf_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qsm_sf_mnoc_cfg },
.link_nodes = { &qsm_sf_mnoc_cfg },
};
static struct qcom_icc_node qss_nsp_qtb_cfg = {
@@ -1102,7 +1102,7 @@ static struct qcom_icc_node qss_pcie_anoc_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qsm_pcie_anoc_cfg },
.link_nodes = { &qsm_pcie_anoc_cfg },
};
static struct qcom_icc_node qss_wlan_q6_throttle_cfg = {
@@ -1201,7 +1201,7 @@ static struct qcom_icc_node qss_cfg = {
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qsm_cfg },
.link_nodes = { &qsm_cfg },
};
static struct qcom_icc_node qss_ddrss_cfg = {
@@ -1251,7 +1251,7 @@ static struct qcom_icc_node qns_gem_noc_cnoc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_cnoc },
.link_nodes = { &qnm_gemnoc_cnoc },
};
static struct qcom_icc_node qns_llcc = {
@@ -1259,7 +1259,7 @@ static struct qcom_icc_node qns_llcc = {
.channels = 2,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &llcc_mc },
.link_nodes = { &llcc_mc },
};
static struct qcom_icc_node qns_pcie = {
@@ -1267,7 +1267,7 @@ static struct qcom_icc_node qns_pcie = {
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_pcie },
.link_nodes = { &qnm_gemnoc_pcie },
};
static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
@@ -1275,7 +1275,7 @@ static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass_gemnoc },
.link_nodes = { &qnm_lpass_gemnoc },
};
static struct qcom_icc_node ebi = {
@@ -1290,7 +1290,7 @@ static struct qcom_icc_node qns_mem_noc_hf = {
.channels = 2,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf },
.link_nodes = { &qnm_mnoc_hf },
};
static struct qcom_icc_node qns_mem_noc_sf = {
@@ -1298,7 +1298,7 @@ static struct qcom_icc_node qns_mem_noc_sf = {
.channels = 2,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf },
.link_nodes = { &qnm_mnoc_sf },
};
static struct qcom_icc_node srvc_mnoc_hf = {
@@ -1320,7 +1320,7 @@ static struct qcom_icc_node qns_nsp_gemnoc = {
.channels = 2,
.buswidth = 32,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_nsp_gemnoc },
.link_nodes = { &qnm_nsp_gemnoc },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
@@ -1328,7 +1328,7 @@ static struct qcom_icc_node qns_pcie_mem_noc = {
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_pcie },
.link_nodes = { &qnm_pcie },
};
static struct qcom_icc_node srvc_pcie_aggre_noc = {
@@ -1343,7 +1343,7 @@ static struct qcom_icc_node qns_gemnoc_gc = {
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_gc },
.link_nodes = { &qnm_snoc_gc },
};
static struct qcom_icc_node qns_gemnoc_sf = {
@@ -1351,7 +1351,7 @@ static struct qcom_icc_node qns_gemnoc_sf = {
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_sf },
.link_nodes = { &qnm_snoc_sf },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1522,7 +1522,6 @@ static const struct qcom_icc_desc milos_aggre1_noc = {
.config = &milos_aggre1_noc_regmap_config,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
@@ -1556,7 +1555,6 @@ static const struct qcom_icc_desc milos_aggre2_noc = {
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
@@ -1576,7 +1574,6 @@ static const struct qcom_icc_desc milos_clk_virt = {
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = {
@@ -1637,7 +1634,6 @@ static const struct qcom_icc_desc milos_cnoc_cfg = {
.num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
.bcms = cnoc_cfg_bcms,
.num_bcms = ARRAY_SIZE(cnoc_cfg_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
@@ -1680,7 +1676,6 @@ static const struct qcom_icc_desc milos_cnoc_main = {
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
.num_bcms = ARRAY_SIZE(cnoc_main_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
@@ -1721,7 +1716,6 @@ static const struct qcom_icc_desc milos_gem_noc = {
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
@@ -1741,7 +1735,6 @@ static const struct qcom_icc_desc milos_lpass_ag_noc = {
.config = &milos_lpass_ag_noc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
@@ -1759,7 +1752,6 @@ static const struct qcom_icc_desc milos_mc_virt = {
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
@@ -1795,7 +1787,6 @@ static const struct qcom_icc_desc milos_mmss_noc = {
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
@@ -1821,7 +1812,6 @@ static const struct qcom_icc_desc milos_nsp_noc = {
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
@@ -1850,7 +1840,6 @@ static const struct qcom_icc_desc milos_pcie_anoc = {
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
.alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const system_noc_bcms[] = {
@@ -1885,7 +1874,6 @@ static const struct qcom_icc_desc milos_system_noc = {
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
.alloc_dyn_id = true,
};
static const struct of_device_id qnoc_of_match[] = {

1
drivers/interconnect/qcom/msm8996.c
View File

@@ -552,6 +552,7 @@ static struct qcom_icc_node mas_venus_vmem = {
static const u16 mas_snoc_pnoc_links[] = {
MSM8996_SLAVE_BLSP_1,
MSM8996_SLAVE_BLSP_2,
MSM8996_SLAVE_USB_HS,
MSM8996_SLAVE_SDCC_1,
MSM8996_SLAVE_SDCC_2,
MSM8996_SLAVE_SDCC_4,

511
drivers/interconnect/qcom/qcs615.c
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File diff suppressed because it is too large Load Diff

128
drivers/interconnect/qcom/qcs615.h
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@@ -1,128 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_QCS615_H
#define __DRIVERS_INTERCONNECT_QCOM_QCS615_H
#define QCS615_MASTER_A1NOC_CFG 1
#define QCS615_MASTER_A1NOC_SNOC 2
#define QCS615_MASTER_ANOC_PCIE_SNOC 3
#define QCS615_MASTER_APPSS_PROC 4
#define QCS615_MASTER_BLSP_1 5
#define QCS615_MASTER_CAMNOC_HF0 6
#define QCS615_MASTER_CAMNOC_HF0_UNCOMP 7
#define QCS615_MASTER_CAMNOC_HF1 8
#define QCS615_MASTER_CAMNOC_HF1_UNCOMP 9
#define QCS615_MASTER_CAMNOC_SF 10
#define QCS615_MASTER_CAMNOC_SF_UNCOMP 11
#define QCS615_MASTER_CNOC_A2NOC 12
#define QCS615_MASTER_CNOC_DC_NOC 13
#define QCS615_MASTER_CNOC_MNOC_CFG 14
#define QCS615_MASTER_CRYPTO 15
#define QCS615_MASTER_EMAC_EVB 16
#define QCS615_MASTER_GEM_NOC_CFG 17
#define QCS615_MASTER_GEM_NOC_PCIE_SNOC 18
#define QCS615_MASTER_GEM_NOC_SNOC 19
#define QCS615_MASTER_GFX3D 20
#define QCS615_MASTER_GIC 21
#define QCS615_MASTER_GPU_TCU 22
#define QCS615_MASTER_IPA 23
#define QCS615_MASTER_IPA_CORE 24
#define QCS615_MASTER_LLCC 25
#define QCS615_MASTER_LPASS_ANOC 26
#define QCS615_MASTER_MDP0 27
#define QCS615_MASTER_MNOC_HF_MEM_NOC 28
#define QCS615_MASTER_MNOC_SF_MEM_NOC 29
#define QCS615_MASTER_PCIE 30
#define QCS615_MASTER_PIMEM 31
#define QCS615_MASTER_QDSS_BAM 32
#define QCS615_MASTER_QDSS_DAP 33
#define QCS615_MASTER_QDSS_ETR 34
#define QCS615_MASTER_QSPI 35
#define QCS615_MASTER_QUP_0 36
#define QCS615_MASTER_ROTATOR 37
#define QCS615_MASTER_SDCC_1 38
#define QCS615_MASTER_SDCC_2 39
#define QCS615_MASTER_SNOC_CFG 40
#define QCS615_MASTER_SNOC_CNOC 41
#define QCS615_MASTER_SNOC_GC_MEM_NOC 42
#define QCS615_MASTER_SNOC_SF_MEM_NOC 43
#define QCS615_MASTER_SPDM 44
#define QCS615_MASTER_SYS_TCU 45
#define QCS615_MASTER_UFS_MEM 46
#define QCS615_MASTER_USB2 47
#define QCS615_MASTER_USB3_0 48
#define QCS615_MASTER_VIDEO_P0 49
#define QCS615_MASTER_VIDEO_PROC 50
#define QCS615_SLAVE_A1NOC_CFG 51
#define QCS615_SLAVE_A1NOC_SNOC 52
#define QCS615_SLAVE_AHB2PHY_EAST 53
#define QCS615_SLAVE_AHB2PHY_WEST 54
#define QCS615_SLAVE_ANOC_PCIE_SNOC 55
#define QCS615_SLAVE_AOP 56
#define QCS615_SLAVE_AOSS 57
#define QCS615_SLAVE_APPSS 58
#define QCS615_SLAVE_CAMERA_CFG 59
#define QCS615_SLAVE_CAMNOC_UNCOMP 60
#define QCS615_SLAVE_CLK_CTL 61
#define QCS615_SLAVE_CNOC_A2NOC 62
#define QCS615_SLAVE_CNOC_DDRSS 63
#define QCS615_SLAVE_CNOC_MNOC_CFG 64
#define QCS615_SLAVE_CRYPTO_0_CFG 65
#define QCS615_SLAVE_DC_NOC_GEMNOC 66
#define QCS615_SLAVE_DISPLAY_CFG 67
#define QCS615_SLAVE_EBI1 68
#define QCS615_SLAVE_EMAC_AVB_CFG 69
#define QCS615_SLAVE_GEM_NOC_SNOC 70
#define QCS615_SLAVE_GFX3D_CFG 71
#define QCS615_SLAVE_GLM 72
#define QCS615_SLAVE_IMEM 73
#define QCS615_SLAVE_IMEM_CFG 74
#define QCS615_SLAVE_IPA_CFG 75
#define QCS615_SLAVE_IPA_CORE 76
#define QCS615_SLAVE_LLCC 77
#define QCS615_SLAVE_LLCC_CFG 78
#define QCS615_SLAVE_LPASS_SNOC 79
#define QCS615_SLAVE_MEM_NOC_PCIE_SNOC 80
#define QCS615_SLAVE_MNOC_HF_MEM_NOC 81
#define QCS615_SLAVE_MNOC_SF_MEM_NOC 82
#define QCS615_SLAVE_MSS_PROC_MS_MPU_CFG 83
#define QCS615_SLAVE_PCIE_0 84
#define QCS615_SLAVE_PCIE_CFG 85
#define QCS615_SLAVE_PIMEM 86
#define QCS615_SLAVE_PIMEM_CFG 87
#define QCS615_SLAVE_PRNG 88
#define QCS615_SLAVE_QDSS_CFG 89
#define QCS615_SLAVE_QDSS_STM 90
#define QCS615_SLAVE_QSPI 91
#define QCS615_SLAVE_QUP_0 92
#define QCS615_SLAVE_QUP_1 93
#define QCS615_SLAVE_RBCPR_CX_CFG 94
#define QCS615_SLAVE_RBCPR_MX_CFG 95
#define QCS615_SLAVE_SDCC_1 96
#define QCS615_SLAVE_SDCC_2 97
#define QCS615_SLAVE_SERVICE_A2NOC 98
#define QCS615_SLAVE_SERVICE_CNOC 99
#define QCS615_SLAVE_SERVICE_GEM_NOC 100
#define QCS615_SLAVE_SERVICE_MNOC 101
#define QCS615_SLAVE_SERVICE_SNOC 102
#define QCS615_SLAVE_SNOC_CFG 103
#define QCS615_SLAVE_SNOC_CNOC 104
#define QCS615_SLAVE_SNOC_GEM_NOC_SF 105
#define QCS615_SLAVE_SNOC_MEM_NOC_GC 106
#define QCS615_SLAVE_SPDM_WRAPPER 107
#define QCS615_SLAVE_TCSR 108
#define QCS615_SLAVE_TCU 109
#define QCS615_SLAVE_TLMM_EAST 110
#define QCS615_SLAVE_TLMM_SOUTH 111
#define QCS615_SLAVE_TLMM_WEST 112
#define QCS615_SLAVE_UFS_MEM_CFG 113
#define QCS615_SLAVE_USB2 114
#define QCS615_SLAVE_USB3 115
#define QCS615_SLAVE_VENUS_CFG 116
#define QCS615_SLAVE_VSENSE_CTRL_CFG 117
#endif

671
drivers/interconnect/qcom/qcs8300.c
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File diff suppressed because it is too large Load Diff

177
drivers/interconnect/qcom/qcs8300.h
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@@ -1,177 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_QCS8300_H
#define __DRIVERS_INTERCONNECT_QCOM_QCS8300_H
#define QCS8300_MASTER_GPU_TCU 0
#define QCS8300_MASTER_PCIE_TCU 1
#define QCS8300_MASTER_SYS_TCU 2
#define QCS8300_MASTER_APPSS_PROC 3
#define QCS8300_MASTER_LLCC 4
#define QCS8300_MASTER_CNOC_LPASS_AG_NOC 5
#define QCS8300_MASTER_GIC_AHB 6
#define QCS8300_MASTER_CDSP_NOC_CFG 7
#define QCS8300_MASTER_QDSS_BAM 8
#define QCS8300_MASTER_QUP_0 9
#define QCS8300_MASTER_QUP_1 10
#define QCS8300_MASTER_A1NOC_SNOC 11
#define QCS8300_MASTER_A2NOC_SNOC 12
#define QCS8300_MASTER_CAMNOC_HF 13
#define QCS8300_MASTER_CAMNOC_ICP 14
#define QCS8300_MASTER_CAMNOC_SF 15
#define QCS8300_MASTER_COMPUTE_NOC 16
#define QCS8300_MASTER_CNOC_A2NOC 17
#define QCS8300_MASTER_CNOC_DC_NOC 18
#define QCS8300_MASTER_GEM_NOC_CFG 19
#define QCS8300_MASTER_GEM_NOC_CNOC 20
#define QCS8300_MASTER_GEM_NOC_PCIE_SNOC 21
#define QCS8300_MASTER_GPDSP_SAIL 22
#define QCS8300_MASTER_GFX3D 23
#define QCS8300_MASTER_LPASS_ANOC 24
#define QCS8300_MASTER_MDP0 25
#define QCS8300_MASTER_MDP1 26
#define QCS8300_MASTER_MNOC_HF_MEM_NOC 27
#define QCS8300_MASTER_CNOC_MNOC_HF_CFG 28
#define QCS8300_MASTER_MNOC_SF_MEM_NOC 29
#define QCS8300_MASTER_CNOC_MNOC_SF_CFG 30
#define QCS8300_MASTER_ANOC_PCIE_GEM_NOC 31
#define QCS8300_MASTER_SAILSS_MD0 32
#define QCS8300_MASTER_SNOC_CFG 33
#define QCS8300_MASTER_SNOC_GC_MEM_NOC 34
#define QCS8300_MASTER_SNOC_SF_MEM_NOC 35
#define QCS8300_MASTER_VIDEO_P0 36
#define QCS8300_MASTER_VIDEO_PROC 37
#define QCS8300_MASTER_VIDEO_V_PROC 38
#define QCS8300_MASTER_QUP_CORE_0 39
#define QCS8300_MASTER_QUP_CORE_1 40
#define QCS8300_MASTER_QUP_CORE_3 41
#define QCS8300_MASTER_CRYPTO_CORE0 42
#define QCS8300_MASTER_CRYPTO_CORE1 43
#define QCS8300_MASTER_DSP0 44
#define QCS8300_MASTER_IPA 45
#define QCS8300_MASTER_LPASS_PROC 46
#define QCS8300_MASTER_CDSP_PROC 47
#define QCS8300_MASTER_PIMEM 48
#define QCS8300_MASTER_QUP_3 49
#define QCS8300_MASTER_EMAC 50
#define QCS8300_MASTER_GIC 51
#define QCS8300_MASTER_PCIE_0 52
#define QCS8300_MASTER_PCIE_1 53
#define QCS8300_MASTER_QDSS_ETR_0 54
#define QCS8300_MASTER_QDSS_ETR_1 55
#define QCS8300_MASTER_SDC 56
#define QCS8300_MASTER_UFS_MEM 57
#define QCS8300_MASTER_USB2 58
#define QCS8300_MASTER_USB3_0 59
#define QCS8300_SLAVE_EBI1 60
#define QCS8300_SLAVE_AHB2PHY_2 61
#define QCS8300_SLAVE_AHB2PHY_3 62
#define QCS8300_SLAVE_ANOC_THROTTLE_CFG 63
#define QCS8300_SLAVE_AOSS 64
#define QCS8300_SLAVE_APPSS 65
#define QCS8300_SLAVE_BOOT_ROM 66
#define QCS8300_SLAVE_CAMERA_CFG 67
#define QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG 68
#define QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG 69
#define QCS8300_SLAVE_CLK_CTL 70
#define QCS8300_SLAVE_CDSP_CFG 71
#define QCS8300_SLAVE_RBCPR_CX_CFG 72
#define QCS8300_SLAVE_RBCPR_MMCX_CFG 73
#define QCS8300_SLAVE_RBCPR_MX_CFG 74
#define QCS8300_SLAVE_CPR_NSPCX 75
#define QCS8300_SLAVE_CPR_NSPHMX 76
#define QCS8300_SLAVE_CRYPTO_0_CFG 77
#define QCS8300_SLAVE_CX_RDPM 78
#define QCS8300_SLAVE_DISPLAY_CFG 79
#define QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG 80
#define QCS8300_SLAVE_EMAC_CFG 81
#define QCS8300_SLAVE_GP_DSP0_CFG 82
#define QCS8300_SLAVE_GPDSP0_THROTTLE_CFG 83
#define QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG 84
#define QCS8300_SLAVE_GFX3D_CFG 85
#define QCS8300_SLAVE_HWKM 86
#define QCS8300_SLAVE_IMEM_CFG 87
#define QCS8300_SLAVE_IPA_CFG 88
#define QCS8300_SLAVE_IPC_ROUTER_CFG 89
#define QCS8300_SLAVE_LLCC_CFG 90
#define QCS8300_SLAVE_LPASS 91
#define QCS8300_SLAVE_LPASS_CORE_CFG 92
#define QCS8300_SLAVE_LPASS_LPI_CFG 93
#define QCS8300_SLAVE_LPASS_MPU_CFG 94
#define QCS8300_SLAVE_LPASS_THROTTLE_CFG 95
#define QCS8300_SLAVE_LPASS_TOP_CFG 96
#define QCS8300_SLAVE_MX_RDPM 97
#define QCS8300_SLAVE_MXC_RDPM 98
#define QCS8300_SLAVE_PCIE_0_CFG 99
#define QCS8300_SLAVE_PCIE_1_CFG 100
#define QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG 101
#define QCS8300_SLAVE_PCIE_THROTTLE_CFG 102
#define QCS8300_SLAVE_PDM 103
#define QCS8300_SLAVE_PIMEM_CFG 104
#define QCS8300_SLAVE_PKA_WRAPPER_CFG 105
#define QCS8300_SLAVE_QDSS_CFG 106
#define QCS8300_SLAVE_QM_CFG 107
#define QCS8300_SLAVE_QM_MPU_CFG 108
#define QCS8300_SLAVE_QUP_0 109
#define QCS8300_SLAVE_QUP_1 110
#define QCS8300_SLAVE_QUP_3 111
#define QCS8300_SLAVE_SAIL_THROTTLE_CFG 112
#define QCS8300_SLAVE_SDC1 113
#define QCS8300_SLAVE_SECURITY 114
#define QCS8300_SLAVE_SNOC_THROTTLE_CFG 115
#define QCS8300_SLAVE_TCSR 116
#define QCS8300_SLAVE_TLMM 117
#define QCS8300_SLAVE_TSC_CFG 118
#define QCS8300_SLAVE_UFS_MEM_CFG 119
#define QCS8300_SLAVE_USB2 120
#define QCS8300_SLAVE_USB3_0 121
#define QCS8300_SLAVE_VENUS_CFG 122
#define QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG 123
#define QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG 124
#define QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG 125
#define QCS8300_SLAVE_A1NOC_SNOC 126
#define QCS8300_SLAVE_A2NOC_SNOC 127
#define QCS8300_SLAVE_DDRSS_CFG 128
#define QCS8300_SLAVE_GEM_NOC_CNOC 129
#define QCS8300_SLAVE_GEM_NOC_CFG 130
#define QCS8300_SLAVE_SNOC_GEM_NOC_GC 131
#define QCS8300_SLAVE_SNOC_GEM_NOC_SF 132
#define QCS8300_SLAVE_GP_DSP_SAIL_NOC 133
#define QCS8300_SLAVE_GPDSP_NOC_CFG 134
#define QCS8300_SLAVE_HCP_A 135
#define QCS8300_SLAVE_LLCC 136
#define QCS8300_SLAVE_MNOC_HF_MEM_NOC 137
#define QCS8300_SLAVE_MNOC_SF_MEM_NOC 138
#define QCS8300_SLAVE_CNOC_MNOC_HF_CFG 139
#define QCS8300_SLAVE_CNOC_MNOC_SF_CFG 140
#define QCS8300_SLAVE_CDSP_MEM_NOC 141
#define QCS8300_SLAVE_GEM_NOC_PCIE_CNOC 142
#define QCS8300_SLAVE_PCIE_ANOC_CFG 143
#define QCS8300_SLAVE_ANOC_PCIE_GEM_NOC 144
#define QCS8300_SLAVE_SNOC_CFG 145
#define QCS8300_SLAVE_LPASS_SNOC 146
#define QCS8300_SLAVE_QUP_CORE_0 147
#define QCS8300_SLAVE_QUP_CORE_1 148
#define QCS8300_SLAVE_QUP_CORE_3 149
#define QCS8300_SLAVE_BOOT_IMEM 150
#define QCS8300_SLAVE_IMEM 151
#define QCS8300_SLAVE_PIMEM 152
#define QCS8300_SLAVE_SERVICE_NSP_NOC 153
#define QCS8300_SLAVE_SERVICE_GEM_NOC_1 154
#define QCS8300_SLAVE_SERVICE_MNOC_HF 155
#define QCS8300_SLAVE_SERVICE_MNOC_SF 156
#define QCS8300_SLAVE_SERVICES_LPASS_AML_NOC 157
#define QCS8300_SLAVE_SERVICE_LPASS_AG_NOC 158
#define QCS8300_SLAVE_SERVICE_GEM_NOC_2 159
#define QCS8300_SLAVE_SERVICE_SNOC 160
#define QCS8300_SLAVE_SERVICE_GEM_NOC 161
#define QCS8300_SLAVE_SERVICE_GEM_NOC2 162
#define QCS8300_SLAVE_PCIE_0 163
#define QCS8300_SLAVE_PCIE_1 164
#define QCS8300_SLAVE_QDSS_STM 165
#define QCS8300_SLAVE_TCU 166
#endif

348
drivers/interconnect/qcom/qdu1000.c
View File

@@ -15,756 +15,710 @@
#include "bcm-voter.h"
#include "icc-common.h"
#include "icc-rpmh.h"
#include "qdu1000.h"
static struct qcom_icc_node qup0_core_master;
static struct qcom_icc_node qup1_core_master;
static struct qcom_icc_node alm_sys_tcu;
static struct qcom_icc_node chm_apps;
static struct qcom_icc_node qnm_ecpri_dma;
static struct qcom_icc_node qnm_fec_2_gemnoc;
static struct qcom_icc_node qnm_pcie;
static struct qcom_icc_node qnm_snoc_gc;
static struct qcom_icc_node qnm_snoc_sf;
static struct qcom_icc_node qxm_mdsp;
static struct qcom_icc_node llcc_mc;
static struct qcom_icc_node qhm_gic;
static struct qcom_icc_node qhm_qdss_bam;
static struct qcom_icc_node qhm_qpic;
static struct qcom_icc_node qhm_qspi;
static struct qcom_icc_node qhm_qup0;
static struct qcom_icc_node qhm_qup1;
static struct qcom_icc_node qhm_system_noc_cfg;
static struct qcom_icc_node qnm_aggre_noc;
static struct qcom_icc_node qnm_aggre_noc_gsi;
static struct qcom_icc_node qnm_gemnoc_cnoc;
static struct qcom_icc_node qnm_gemnoc_modem_slave;
static struct qcom_icc_node qnm_gemnoc_pcie;
static struct qcom_icc_node qxm_crypto;
static struct qcom_icc_node qxm_ecpri_gsi;
static struct qcom_icc_node qxm_pimem;
static struct qcom_icc_node xm_ecpri_dma;
static struct qcom_icc_node xm_gic;
static struct qcom_icc_node xm_pcie;
static struct qcom_icc_node xm_qdss_etr0;
static struct qcom_icc_node xm_qdss_etr1;
static struct qcom_icc_node xm_sdc;
static struct qcom_icc_node xm_usb3;
static struct qcom_icc_node qup0_core_slave;
static struct qcom_icc_node qup1_core_slave;
static struct qcom_icc_node qns_gem_noc_cnoc;
static struct qcom_icc_node qns_llcc;
static struct qcom_icc_node qns_modem_slave;
static struct qcom_icc_node qns_pcie;
static struct qcom_icc_node ebi;
static struct qcom_icc_node qhs_ahb2phy0_south;
static struct qcom_icc_node qhs_ahb2phy1_north;
static struct qcom_icc_node qhs_ahb2phy2_east;
static struct qcom_icc_node qhs_aoss;
static struct qcom_icc_node qhs_clk_ctl;
static struct qcom_icc_node qhs_cpr_cx;
static struct qcom_icc_node qhs_cpr_mx;
static struct qcom_icc_node qhs_crypto_cfg;
static struct qcom_icc_node qhs_ecpri_cfg;
static struct qcom_icc_node qhs_imem_cfg;
static struct qcom_icc_node qhs_ipc_router;
static struct qcom_icc_node qhs_mss_cfg;
static struct qcom_icc_node qhs_pcie_cfg;
static struct qcom_icc_node qhs_pdm;
static struct qcom_icc_node qhs_pimem_cfg;
static struct qcom_icc_node qhs_prng;
static struct qcom_icc_node qhs_qdss_cfg;
static struct qcom_icc_node qhs_qpic;
static struct qcom_icc_node qhs_qspi;
static struct qcom_icc_node qhs_qup0;
static struct qcom_icc_node qhs_qup1;
static struct qcom_icc_node qhs_sdc2;
static struct qcom_icc_node qhs_smbus_cfg;
static struct qcom_icc_node qhs_system_noc_cfg;
static struct qcom_icc_node qhs_tcsr;
static struct qcom_icc_node qhs_tlmm;
static struct qcom_icc_node qhs_tme_cfg;
static struct qcom_icc_node qhs_tsc_cfg;
static struct qcom_icc_node qhs_usb3;
static struct qcom_icc_node qhs_vsense_ctrl_cfg;
static struct qcom_icc_node qns_a1noc_snoc;
static struct qcom_icc_node qns_anoc_snoc_gsi;
static struct qcom_icc_node qns_ddrss_cfg;
static struct qcom_icc_node qns_ecpri_gemnoc;
static struct qcom_icc_node qns_gemnoc_gc;
static struct qcom_icc_node qns_gemnoc_sf;
static struct qcom_icc_node qns_modem;
static struct qcom_icc_node qns_pcie_gemnoc;
static struct qcom_icc_node qxs_imem;
static struct qcom_icc_node qxs_pimem;
static struct qcom_icc_node srvc_system_noc;
static struct qcom_icc_node xs_ethernet_ss;
static struct qcom_icc_node xs_pcie;
static struct qcom_icc_node xs_qdss_stm;
static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
.id = QDU1000_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_QUP_CORE_0 },
.link_nodes = { &qup0_core_slave },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
.id = QDU1000_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_QUP_CORE_1 },
.link_nodes = { &qup1_core_slave },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
.id = QDU1000_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
.num_links = 2,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
.id = QDU1000_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 16,
.num_links = 4,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
},
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
&qns_modem_slave, &qns_pcie },
};
static struct qcom_icc_node qnm_ecpri_dma = {
.name = "qnm_ecpri_dma",
.id = QDU1000_MASTER_GEMNOC_ECPRI_DMA,
.channels = 2,
.buswidth = 32,
.num_links = 2,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_fec_2_gemnoc = {
.name = "qnm_fec_2_gemnoc",
.id = QDU1000_MASTER_FEC_2_GEMNOC,
.channels = 2,
.buswidth = 32,
.num_links = 2,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
.id = QDU1000_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 64,
.num_links = 3,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
QDU1000_SLAVE_GEMNOC_MODEM_CNOC
},
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
&qns_modem_slave },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
.id = QDU1000_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_SLAVE_LLCC },
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
.id = QDU1000_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 4,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
},
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
&qns_modem_slave, &qns_pcie },
};
static struct qcom_icc_node qxm_mdsp = {
.name = "qxm_mdsp",
.id = QDU1000_MASTER_MSS_PROC,
.channels = 1,
.buswidth = 16,
.num_links = 3,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
},
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
&qns_pcie },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
.id = QDU1000_MASTER_LLCC,
.channels = 8,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_EBI1 },
.link_nodes = { &ebi },
};
static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
.id = QDU1000_MASTER_GIC_AHB,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.id = QDU1000_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
.id = QDU1000_MASTER_QPIC,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_A1NOC_SNOC },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
.id = QDU1000_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_A1NOC_SNOC },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
.id = QDU1000_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_A1NOC_SNOC },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
.id = QDU1000_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_A1NOC_SNOC },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node qhm_system_noc_cfg = {
.name = "qhm_system_noc_cfg",
.id = QDU1000_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_SERVICE_SNOC },
.link_nodes = { &srvc_system_noc },
};
static struct qcom_icc_node qnm_aggre_noc = {
.name = "qnm_aggre_noc",
.id = QDU1000_MASTER_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qnm_aggre_noc_gsi = {
.name = "qnm_aggre_noc_gsi",
.id = QDU1000_MASTER_ANOC_GSI,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC },
.link_nodes = { &qns_gemnoc_gc },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
.id = QDU1000_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
.num_links = 36,
.links = { QDU1000_SLAVE_AHB2PHY_SOUTH, QDU1000_SLAVE_AHB2PHY_NORTH,
QDU1000_SLAVE_AHB2PHY_EAST, QDU1000_SLAVE_AOSS,
QDU1000_SLAVE_CLK_CTL, QDU1000_SLAVE_RBCPR_CX_CFG,
QDU1000_SLAVE_RBCPR_MX_CFG, QDU1000_SLAVE_CRYPTO_0_CFG,
QDU1000_SLAVE_ECPRI_CFG, QDU1000_SLAVE_IMEM_CFG,
QDU1000_SLAVE_IPC_ROUTER_CFG, QDU1000_SLAVE_CNOC_MSS,
QDU1000_SLAVE_PCIE_CFG, QDU1000_SLAVE_PDM,
QDU1000_SLAVE_PIMEM_CFG, QDU1000_SLAVE_PRNG,
QDU1000_SLAVE_QDSS_CFG, QDU1000_SLAVE_QPIC,
QDU1000_SLAVE_QSPI_0, QDU1000_SLAVE_QUP_0,
QDU1000_SLAVE_QUP_1, QDU1000_SLAVE_SDCC_2,
QDU1000_SLAVE_SMBUS_CFG, QDU1000_SLAVE_SNOC_CFG,
QDU1000_SLAVE_TCSR, QDU1000_SLAVE_TLMM,
QDU1000_SLAVE_TME_CFG, QDU1000_SLAVE_TSC_CFG,
QDU1000_SLAVE_USB3_0, QDU1000_SLAVE_VSENSE_CTRL_CFG,
QDU1000_SLAVE_DDRSS_CFG, QDU1000_SLAVE_IMEM,
QDU1000_SLAVE_PIMEM, QDU1000_SLAVE_ETHERNET_SS,
QDU1000_SLAVE_QDSS_STM, QDU1000_SLAVE_TCU
},
.link_nodes = { &qhs_ahb2phy0_south, &qhs_ahb2phy1_north,
&qhs_ahb2phy2_east, &qhs_aoss,
&qhs_clk_ctl, &qhs_cpr_cx,
&qhs_cpr_mx, &qhs_crypto_cfg,
&qhs_ecpri_cfg, &qhs_imem_cfg,
&qhs_ipc_router, &qhs_mss_cfg,
&qhs_pcie_cfg, &qhs_pdm,
&qhs_pimem_cfg, &qhs_prng,
&qhs_qdss_cfg, &qhs_qpic,
&qhs_qspi, &qhs_qup0,
&qhs_qup1, &qhs_sdc2,
&qhs_smbus_cfg, &qhs_system_noc_cfg,
&qhs_tcsr, &qhs_tlmm,
&qhs_tme_cfg, &qhs_tsc_cfg,
&qhs_usb3, &qhs_vsense_ctrl_cfg,
&qns_ddrss_cfg, &qxs_imem,
&qxs_pimem, &xs_ethernet_ss,
&xs_qdss_stm, &xs_sys_tcu_cfg },
};
static struct qcom_icc_node qnm_gemnoc_modem_slave = {
.name = "qnm_gemnoc_modem_slave",
.id = QDU1000_MASTER_GEMNOC_MODEM_CNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { QDU1000_SLAVE_MODEM_OFFLINE },
.link_nodes = { &qns_modem },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
.id = QDU1000_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { QDU1000_SLAVE_PCIE_0 },
.link_nodes = { &xs_pcie },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
.id = QDU1000_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_SLAVE_A1NOC_SNOC },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node qxm_ecpri_gsi = {
.name = "qxm_ecpri_gsi",
.id = QDU1000_MASTER_ECPRI_GSI,
.channels = 1,
.buswidth = 8,
.num_links = 2,
.links = { QDU1000_SLAVE_ANOC_SNOC_GSI, QDU1000_SLAVE_PCIE_0 },
.link_nodes = { &qns_anoc_snoc_gsi, &xs_pcie },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
.id = QDU1000_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC },
.link_nodes = { &qns_gemnoc_gc },
};
static struct qcom_icc_node xm_ecpri_dma = {
.name = "xm_ecpri_dma",
.id = QDU1000_MASTER_SNOC_ECPRI_DMA,
.channels = 2,
.buswidth = 32,
.num_links = 2,
.links = { QDU1000_SLAVE_ECPRI_GEMNOC, QDU1000_SLAVE_PCIE_0 },
.link_nodes = { &qns_ecpri_gemnoc, &xs_pcie },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
.id = QDU1000_MASTER_GIC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC },
.link_nodes = { &qns_gemnoc_gc },
};
static struct qcom_icc_node xm_pcie = {
.name = "xm_pcie",
.id = QDU1000_MASTER_PCIE,
.channels = 1,
.buswidth = 64,
.num_links = 1,
.links = { QDU1000_SLAVE_ANOC_PCIE_GEM_NOC },
.link_nodes = { &qns_pcie_gemnoc },
};
static struct qcom_icc_node xm_qdss_etr0 = {
.name = "xm_qdss_etr0",
.id = QDU1000_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node xm_qdss_etr1 = {
.name = "xm_qdss_etr1",
.id = QDU1000_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node xm_sdc = {
.name = "xm_sdc",
.id = QDU1000_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_SLAVE_A1NOC_SNOC },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_usb3 = {
.name = "xm_usb3",
.id = QDU1000_MASTER_USB3,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_SLAVE_A1NOC_SNOC },
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
.id = QDU1000_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
.id = QDU1000_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
.id = QDU1000_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { QDU1000_MASTER_GEM_NOC_CNOC },
.link_nodes = { &qnm_gemnoc_cnoc },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
.id = QDU1000_SLAVE_LLCC,
.channels = 8,
.buswidth = 16,
.num_links = 1,
.links = { QDU1000_MASTER_LLCC },
.link_nodes = { &llcc_mc },
};
static struct qcom_icc_node qns_modem_slave = {
.name = "qns_modem_slave",
.id = QDU1000_SLAVE_GEMNOC_MODEM_CNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { QDU1000_MASTER_GEMNOC_MODEM_CNOC },
.link_nodes = { &qnm_gemnoc_modem_slave },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
.id = QDU1000_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { QDU1000_MASTER_GEM_NOC_PCIE_SNOC },
.link_nodes = { &qnm_gemnoc_pcie },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
.id = QDU1000_SLAVE_EBI1,
.channels = 8,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ahb2phy0_south = {
.name = "qhs_ahb2phy0_south",
.id = QDU1000_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ahb2phy1_north = {
.name = "qhs_ahb2phy1_north",
.id = QDU1000_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ahb2phy2_east = {
.name = "qhs_ahb2phy2_east",
.id = QDU1000_SLAVE_AHB2PHY_EAST,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
.id = QDU1000_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
.id = QDU1000_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
.id = QDU1000_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
.id = QDU1000_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_crypto_cfg = {
.name = "qhs_crypto_cfg",
.id = QDU1000_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ecpri_cfg = {
.name = "qhs_ecpri_cfg",
.id = QDU1000_SLAVE_ECPRI_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
.id = QDU1000_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
.id = QDU1000_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
.id = QDU1000_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pcie_cfg = {
.name = "qhs_pcie_cfg",
.id = QDU1000_SLAVE_PCIE_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
.id = QDU1000_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
.id = QDU1000_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
.id = QDU1000_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
.id = QDU1000_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qpic = {
.name = "qhs_qpic",
.id = QDU1000_SLAVE_QPIC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
.id = QDU1000_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
.id = QDU1000_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
.id = QDU1000_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
.id = QDU1000_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_smbus_cfg = {
.name = "qhs_smbus_cfg",
.id = QDU1000_SLAVE_SMBUS_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_system_noc_cfg = {
.name = "qhs_system_noc_cfg",
.id = QDU1000_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_MASTER_SNOC_CFG },
.link_nodes = { &qhm_system_noc_cfg },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
.id = QDU1000_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
.id = QDU1000_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_tme_cfg = {
.name = "qhs_tme_cfg",
.id = QDU1000_SLAVE_TME_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_tsc_cfg = {
.name = "qhs_tsc_cfg",
.id = QDU1000_SLAVE_TSC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
.id = QDU1000_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
.id = QDU1000_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
.id = QDU1000_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_MASTER_ANOC_SNOC },
.link_nodes = { &qnm_aggre_noc },
};
static struct qcom_icc_node qns_anoc_snoc_gsi = {
.name = "qns_anoc_snoc_gsi",
.id = QDU1000_SLAVE_ANOC_SNOC_GSI,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_MASTER_ANOC_GSI },
.link_nodes = { &qnm_aggre_noc_gsi },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
.id = QDU1000_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_ecpri_gemnoc = {
.name = "qns_ecpri_gemnoc",
.id = QDU1000_SLAVE_ECPRI_GEMNOC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
.links = { QDU1000_MASTER_GEMNOC_ECPRI_DMA },
.link_nodes = { &qnm_ecpri_dma },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
.id = QDU1000_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_MASTER_SNOC_GC_MEM_NOC },
.link_nodes = { &qnm_snoc_gc },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
.id = QDU1000_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { QDU1000_MASTER_SNOC_SF_MEM_NOC },
.link_nodes = { &qnm_snoc_sf },
};
static struct qcom_icc_node qns_modem = {
.name = "qns_modem",
.id = QDU1000_SLAVE_MODEM_OFFLINE,
.channels = 1,
.buswidth = 32,
.num_links = 0,
};
static struct qcom_icc_node qns_pcie_gemnoc = {
.name = "qns_pcie_gemnoc",
.id = QDU1000_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 64,
.num_links = 1,
.links = { QDU1000_MASTER_ANOC_PCIE_GEM_NOC },
.link_nodes = { &qnm_pcie },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
.id = QDU1000_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
.id = QDU1000_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node srvc_system_noc = {
.name = "srvc_system_noc",
.id = QDU1000_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node xs_ethernet_ss = {
.name = "xs_ethernet_ss",
.id = QDU1000_SLAVE_ETHERNET_SS,
.channels = 1,
.buswidth = 32,
.num_links = 0,
};
static struct qcom_icc_node xs_pcie = {
.name = "xs_pcie",
.id = QDU1000_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 64,
.num_links = 0,
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
.id = QDU1000_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
.id = QDU1000_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_bcm bcm_acv = {

95
drivers/interconnect/qcom/qdu1000.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_QDU1000_H
#define __DRIVERS_INTERCONNECT_QCOM_QDU1000_H
#define QDU1000_MASTER_SYS_TCU 0
#define QDU1000_MASTER_APPSS_PROC 1
#define QDU1000_MASTER_LLCC 2
#define QDU1000_MASTER_GIC_AHB 3
#define QDU1000_MASTER_QDSS_BAM 4
#define QDU1000_MASTER_QPIC 5
#define QDU1000_MASTER_QSPI_0 6
#define QDU1000_MASTER_QUP_0 7
#define QDU1000_MASTER_QUP_1 8
#define QDU1000_MASTER_SNOC_CFG 9
#define QDU1000_MASTER_ANOC_SNOC 10
#define QDU1000_MASTER_ANOC_GSI 11
#define QDU1000_MASTER_GEMNOC_ECPRI_DMA 12
#define QDU1000_MASTER_FEC_2_GEMNOC 13
#define QDU1000_MASTER_GEM_NOC_CNOC 14
#define QDU1000_MASTER_GEMNOC_MODEM_CNOC 15
#define QDU1000_MASTER_GEM_NOC_PCIE_SNOC 16
#define QDU1000_MASTER_ANOC_PCIE_GEM_NOC 17
#define QDU1000_MASTER_SNOC_GC_MEM_NOC 18
#define QDU1000_MASTER_SNOC_SF_MEM_NOC 19
#define QDU1000_MASTER_QUP_CORE_0 20
#define QDU1000_MASTER_QUP_CORE_1 21
#define QDU1000_MASTER_CRYPTO 22
#define QDU1000_MASTER_ECPRI_GSI 23
#define QDU1000_MASTER_MSS_PROC 24
#define QDU1000_MASTER_PIMEM 25
#define QDU1000_MASTER_SNOC_ECPRI_DMA 26
#define QDU1000_MASTER_GIC 27
#define QDU1000_MASTER_PCIE 28
#define QDU1000_MASTER_QDSS_ETR 29
#define QDU1000_MASTER_QDSS_ETR_1 30
#define QDU1000_MASTER_SDCC_1 31
#define QDU1000_MASTER_USB3 32
#define QDU1000_SLAVE_EBI1 512
#define QDU1000_SLAVE_AHB2PHY_SOUTH 513
#define QDU1000_SLAVE_AHB2PHY_NORTH 514
#define QDU1000_SLAVE_AHB2PHY_EAST 515
#define QDU1000_SLAVE_AOSS 516
#define QDU1000_SLAVE_CLK_CTL 517
#define QDU1000_SLAVE_RBCPR_CX_CFG 518
#define QDU1000_SLAVE_RBCPR_MX_CFG 519
#define QDU1000_SLAVE_CRYPTO_0_CFG 520
#define QDU1000_SLAVE_ECPRI_CFG 521
#define QDU1000_SLAVE_IMEM_CFG 522
#define QDU1000_SLAVE_IPC_ROUTER_CFG 523
#define QDU1000_SLAVE_CNOC_MSS 524
#define QDU1000_SLAVE_PCIE_CFG 525
#define QDU1000_SLAVE_PDM 526
#define QDU1000_SLAVE_PIMEM_CFG 527
#define QDU1000_SLAVE_PRNG 528
#define QDU1000_SLAVE_QDSS_CFG 529
#define QDU1000_SLAVE_QPIC 530
#define QDU1000_SLAVE_QSPI_0 531
#define QDU1000_SLAVE_QUP_0 532
#define QDU1000_SLAVE_QUP_1 533
#define QDU1000_SLAVE_SDCC_2 534
#define QDU1000_SLAVE_SMBUS_CFG 535
#define QDU1000_SLAVE_SNOC_CFG 536
#define QDU1000_SLAVE_TCSR 537
#define QDU1000_SLAVE_TLMM 538
#define QDU1000_SLAVE_TME_CFG 539
#define QDU1000_SLAVE_TSC_CFG 540
#define QDU1000_SLAVE_USB3_0 541
#define QDU1000_SLAVE_VSENSE_CTRL_CFG 542
#define QDU1000_SLAVE_A1NOC_SNOC 543
#define QDU1000_SLAVE_ANOC_SNOC_GSI 544
#define QDU1000_SLAVE_DDRSS_CFG 545
#define QDU1000_SLAVE_ECPRI_GEMNOC 546
#define QDU1000_SLAVE_GEM_NOC_CNOC 547
#define QDU1000_SLAVE_SNOC_GEM_NOC_GC 548
#define QDU1000_SLAVE_SNOC_GEM_NOC_SF 549
#define QDU1000_SLAVE_LLCC 550
#define QDU1000_SLAVE_MODEM_OFFLINE 551
#define QDU1000_SLAVE_GEMNOC_MODEM_CNOC 552
#define QDU1000_SLAVE_MEM_NOC_PCIE_SNOC 553
#define QDU1000_SLAVE_ANOC_PCIE_GEM_NOC 554
#define QDU1000_SLAVE_QUP_CORE_0 555
#define QDU1000_SLAVE_QUP_CORE_1 556
#define QDU1000_SLAVE_IMEM 557
#define QDU1000_SLAVE_PIMEM 558
#define QDU1000_SLAVE_SERVICE_SNOC 559
#define QDU1000_SLAVE_ETHERNET_SS 560
#define QDU1000_SLAVE_PCIE_0 561
#define QDU1000_SLAVE_QDSS_STM 562
#define QDU1000_SLAVE_TCU 563
#endif

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drivers/interconnect/qcom/sa8775p.c
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drivers/interconnect/qcom/sar2130p.c
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drivers/interconnect/qcom/sc7180.c
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drivers/interconnect/qcom/sc7180.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm #define SC7180 interconnect IDs
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7180_H
#define __DRIVERS_INTERCONNECT_QCOM_SC7180_H
#define SC7180_MASTER_APPSS_PROC 0
#define SC7180_MASTER_SYS_TCU 1
#define SC7180_MASTER_NPU_SYS 2
/* 3 was used by MASTER_IPA_CORE, now represented as RPMh clock */
#define SC7180_MASTER_LLCC 4
#define SC7180_MASTER_A1NOC_CFG 5
#define SC7180_MASTER_A2NOC_CFG 6
#define SC7180_MASTER_CNOC_DC_NOC 7
#define SC7180_MASTER_GEM_NOC_CFG 8
#define SC7180_MASTER_CNOC_MNOC_CFG 9
#define SC7180_MASTER_NPU_NOC_CFG 10
#define SC7180_MASTER_QDSS_BAM 11
#define SC7180_MASTER_QSPI 12
#define SC7180_MASTER_QUP_0 13
#define SC7180_MASTER_QUP_1 14
#define SC7180_MASTER_SNOC_CFG 15
#define SC7180_MASTER_A1NOC_SNOC 16
#define SC7180_MASTER_A2NOC_SNOC 17
#define SC7180_MASTER_COMPUTE_NOC 18
#define SC7180_MASTER_GEM_NOC_SNOC 19
#define SC7180_MASTER_MNOC_HF_MEM_NOC 20
#define SC7180_MASTER_MNOC_SF_MEM_NOC 21
#define SC7180_MASTER_NPU 22
#define SC7180_MASTER_SNOC_CNOC 23
#define SC7180_MASTER_SNOC_GC_MEM_NOC 24
#define SC7180_MASTER_SNOC_SF_MEM_NOC 25
#define SC7180_MASTER_QUP_CORE_0 26
#define SC7180_MASTER_QUP_CORE_1 27
#define SC7180_MASTER_CAMNOC_HF0 28
#define SC7180_MASTER_CAMNOC_HF1 29
#define SC7180_MASTER_CAMNOC_HF0_UNCOMP 30
#define SC7180_MASTER_CAMNOC_HF1_UNCOMP 31
#define SC7180_MASTER_CAMNOC_SF 32
#define SC7180_MASTER_CAMNOC_SF_UNCOMP 33
#define SC7180_MASTER_CRYPTO 34
#define SC7180_MASTER_GFX3D 35
#define SC7180_MASTER_IPA 36
#define SC7180_MASTER_MDP0 37
#define SC7180_MASTER_NPU_PROC 38
#define SC7180_MASTER_PIMEM 39
#define SC7180_MASTER_ROTATOR 40
#define SC7180_MASTER_VIDEO_P0 41
#define SC7180_MASTER_VIDEO_PROC 42
#define SC7180_MASTER_QDSS_DAP 43
#define SC7180_MASTER_QDSS_ETR 44
#define SC7180_MASTER_SDCC_2 45
#define SC7180_MASTER_UFS_MEM 46
#define SC7180_MASTER_USB3 47
#define SC7180_MASTER_EMMC 48
#define SC7180_SLAVE_EBI1 49
/* 50 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SC7180_SLAVE_A1NOC_CFG 51
#define SC7180_SLAVE_A2NOC_CFG 52
#define SC7180_SLAVE_AHB2PHY_SOUTH 53
#define SC7180_SLAVE_AHB2PHY_CENTER 54
#define SC7180_SLAVE_AOP 55
#define SC7180_SLAVE_AOSS 56
#define SC7180_SLAVE_APPSS 57
#define SC7180_SLAVE_BOOT_ROM 58
#define SC7180_SLAVE_NPU_CAL_DP0 59
#define SC7180_SLAVE_CAMERA_CFG 60
#define SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG 61
#define SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG 62
#define SC7180_SLAVE_CLK_CTL 63
#define SC7180_SLAVE_NPU_CP 64
#define SC7180_SLAVE_RBCPR_CX_CFG 65
#define SC7180_SLAVE_RBCPR_MX_CFG 66
#define SC7180_SLAVE_CRYPTO_0_CFG 67
#define SC7180_SLAVE_DCC_CFG 68
#define SC7180_SLAVE_CNOC_DDRSS 69
#define SC7180_SLAVE_DISPLAY_CFG 70
#define SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG 71
#define SC7180_SLAVE_DISPLAY_THROTTLE_CFG 72
#define SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG 73
#define SC7180_SLAVE_NPU_DPM 74
#define SC7180_SLAVE_EMMC_CFG 75
#define SC7180_SLAVE_GEM_NOC_CFG 76
#define SC7180_SLAVE_GLM 77
#define SC7180_SLAVE_GFX3D_CFG 78
#define SC7180_SLAVE_IMEM_CFG 79
#define SC7180_SLAVE_IPA_CFG 80
#define SC7180_SLAVE_ISENSE_CFG 81
#define SC7180_SLAVE_LLCC_CFG 82
#define SC7180_SLAVE_NPU_LLM_CFG 83
#define SC7180_SLAVE_MSS_PROC_MS_MPU_CFG 84
#define SC7180_SLAVE_CNOC_MNOC_CFG 85
#define SC7180_SLAVE_CNOC_MSS 86
#define SC7180_SLAVE_NPU_CFG 87
#define SC7180_SLAVE_NPU_DMA_BWMON_CFG 88
#define SC7180_SLAVE_NPU_PROC_BWMON_CFG 89
#define SC7180_SLAVE_PDM 90
#define SC7180_SLAVE_PIMEM_CFG 91
#define SC7180_SLAVE_PRNG 92
#define SC7180_SLAVE_QDSS_CFG 93
#define SC7180_SLAVE_QM_CFG 94
#define SC7180_SLAVE_QM_MPU_CFG 95
#define SC7180_SLAVE_QSPI_0 96
#define SC7180_SLAVE_QUP_0 97
#define SC7180_SLAVE_QUP_1 98
#define SC7180_SLAVE_SDCC_2 99
#define SC7180_SLAVE_SECURITY 100
#define SC7180_SLAVE_SNOC_CFG 101
#define SC7180_SLAVE_NPU_TCM 102
#define SC7180_SLAVE_TCSR 103
#define SC7180_SLAVE_TLMM_WEST 104
#define SC7180_SLAVE_TLMM_NORTH 105
#define SC7180_SLAVE_TLMM_SOUTH 106
#define SC7180_SLAVE_UFS_MEM_CFG 107
#define SC7180_SLAVE_USB3 108
#define SC7180_SLAVE_VENUS_CFG 109
#define SC7180_SLAVE_VENUS_THROTTLE_CFG 110
#define SC7180_SLAVE_VSENSE_CTRL_CFG 111
#define SC7180_SLAVE_A1NOC_SNOC 112
#define SC7180_SLAVE_A2NOC_SNOC 113
#define SC7180_SLAVE_CAMNOC_UNCOMP 114
#define SC7180_SLAVE_CDSP_GEM_NOC 115
#define SC7180_SLAVE_SNOC_CNOC 116
#define SC7180_SLAVE_GEM_NOC_SNOC 117
#define SC7180_SLAVE_SNOC_GEM_NOC_GC 118
#define SC7180_SLAVE_SNOC_GEM_NOC_SF 119
#define SC7180_SLAVE_LLCC 120
#define SC7180_SLAVE_MNOC_HF_MEM_NOC 121
#define SC7180_SLAVE_MNOC_SF_MEM_NOC 122
#define SC7180_SLAVE_NPU_COMPUTE_NOC 123
#define SC7180_SLAVE_QUP_CORE_0 124
#define SC7180_SLAVE_QUP_CORE_1 125
#define SC7180_SLAVE_IMEM 126
#define SC7180_SLAVE_PIMEM 127
#define SC7180_SLAVE_SERVICE_A1NOC 128
#define SC7180_SLAVE_SERVICE_A2NOC 129
#define SC7180_SLAVE_SERVICE_CNOC 130
#define SC7180_SLAVE_SERVICE_GEM_NOC 131
#define SC7180_SLAVE_SERVICE_MNOC 132
#define SC7180_SLAVE_SERVICE_NPU_NOC 133
#define SC7180_SLAVE_SERVICE_SNOC 134
#define SC7180_SLAVE_QDSS_STM 135
#define SC7180_SLAVE_TCU 136
#endif

617
drivers/interconnect/qcom/sc7280.c
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drivers/interconnect/qcom/sc7280.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm #define SC7280 interconnect IDs
*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7280_H
#define __DRIVERS_INTERCONNECT_QCOM_SC7280_H
#define SC7280_MASTER_GPU_TCU 0
#define SC7280_MASTER_SYS_TCU 1
#define SC7280_MASTER_APPSS_PROC 2
#define SC7280_MASTER_LLCC 3
#define SC7280_MASTER_CNOC_LPASS_AG_NOC 4
#define SC7280_MASTER_CDSP_NOC_CFG 5
#define SC7280_MASTER_QDSS_BAM 6
#define SC7280_MASTER_QSPI_0 7
#define SC7280_MASTER_QUP_0 8
#define SC7280_MASTER_QUP_1 9
#define SC7280_MASTER_A1NOC_CFG 10
#define SC7280_MASTER_A2NOC_CFG 11
#define SC7280_MASTER_A1NOC_SNOC 12
#define SC7280_MASTER_A2NOC_SNOC 13
#define SC7280_MASTER_COMPUTE_NOC 14
#define SC7280_MASTER_CNOC2_CNOC3 15
#define SC7280_MASTER_CNOC3_CNOC2 16
#define SC7280_MASTER_CNOC_A2NOC 17
#define SC7280_MASTER_CNOC_DC_NOC 18
#define SC7280_MASTER_GEM_NOC_CFG 19
#define SC7280_MASTER_GEM_NOC_CNOC 20
#define SC7280_MASTER_GEM_NOC_PCIE_SNOC 21
#define SC7280_MASTER_GFX3D 22
#define SC7280_MASTER_CNOC_MNOC_CFG 23
#define SC7280_MASTER_MNOC_HF_MEM_NOC 24
#define SC7280_MASTER_MNOC_SF_MEM_NOC 25
#define SC7280_MASTER_ANOC_PCIE_GEM_NOC 26
#define SC7280_MASTER_SNOC_CFG 27
#define SC7280_MASTER_SNOC_GC_MEM_NOC 28
#define SC7280_MASTER_SNOC_SF_MEM_NOC 29
#define SC7280_MASTER_VIDEO_P0 30
#define SC7280_MASTER_VIDEO_PROC 31
#define SC7280_MASTER_QUP_CORE_0 32
#define SC7280_MASTER_QUP_CORE_1 33
#define SC7280_MASTER_CAMNOC_HF 34
#define SC7280_MASTER_CAMNOC_ICP 35
#define SC7280_MASTER_CAMNOC_SF 36
#define SC7280_MASTER_CRYPTO 37
#define SC7280_MASTER_IPA 38
#define SC7280_MASTER_MDP0 39
#define SC7280_MASTER_CDSP_PROC 40
#define SC7280_MASTER_PIMEM 41
#define SC7280_MASTER_GIC 42
#define SC7280_MASTER_PCIE_0 43
#define SC7280_MASTER_PCIE_1 44
#define SC7280_MASTER_QDSS_DAP 45
#define SC7280_MASTER_QDSS_ETR 46
#define SC7280_MASTER_SDCC_1 47
#define SC7280_MASTER_SDCC_2 48
#define SC7280_MASTER_SDCC_4 49
#define SC7280_MASTER_UFS_MEM 50
#define SC7280_MASTER_USB2 51
#define SC7280_MASTER_USB3_0 52
#define SC7280_SLAVE_EBI1 53
#define SC7280_SLAVE_AHB2PHY_SOUTH 54
#define SC7280_SLAVE_AHB2PHY_NORTH 55
#define SC7280_SLAVE_AOSS 56
#define SC7280_SLAVE_APPSS 57
#define SC7280_SLAVE_CAMERA_CFG 58
#define SC7280_SLAVE_CLK_CTL 59
#define SC7280_SLAVE_CDSP_CFG 60
#define SC7280_SLAVE_RBCPR_CX_CFG 61
#define SC7280_SLAVE_RBCPR_MX_CFG 62
#define SC7280_SLAVE_CRYPTO_0_CFG 63
#define SC7280_SLAVE_CX_RDPM 64
#define SC7280_SLAVE_DCC_CFG 65
#define SC7280_SLAVE_DISPLAY_CFG 66
#define SC7280_SLAVE_GFX3D_CFG 67
#define SC7280_SLAVE_HWKM 68
#define SC7280_SLAVE_IMEM_CFG 69
#define SC7280_SLAVE_IPA_CFG 70
#define SC7280_SLAVE_IPC_ROUTER_CFG 71
#define SC7280_SLAVE_LLCC_CFG 72
#define SC7280_SLAVE_LPASS 73
#define SC7280_SLAVE_LPASS_CORE_CFG 74
#define SC7280_SLAVE_LPASS_LPI_CFG 75
#define SC7280_SLAVE_LPASS_MPU_CFG 76
#define SC7280_SLAVE_LPASS_TOP_CFG 77
#define SC7280_SLAVE_MSS_PROC_MS_MPU_CFG 78
#define SC7280_SLAVE_MCDMA_MS_MPU_CFG 79
#define SC7280_SLAVE_CNOC_MSS 80
#define SC7280_SLAVE_MX_RDPM 81
#define SC7280_SLAVE_PCIE_0_CFG 82
#define SC7280_SLAVE_PCIE_1_CFG 83
#define SC7280_SLAVE_PDM 84
#define SC7280_SLAVE_PIMEM_CFG 85
#define SC7280_SLAVE_PKA_WRAPPER_CFG 86
#define SC7280_SLAVE_PMU_WRAPPER_CFG 87
#define SC7280_SLAVE_QDSS_CFG 88
#define SC7280_SLAVE_QSPI_0 89
#define SC7280_SLAVE_QUP_0 90
#define SC7280_SLAVE_QUP_1 91
#define SC7280_SLAVE_SDCC_1 92
#define SC7280_SLAVE_SDCC_2 93
#define SC7280_SLAVE_SDCC_4 94
#define SC7280_SLAVE_SECURITY 95
#define SC7280_SLAVE_TCSR 96
#define SC7280_SLAVE_TLMM 97
#define SC7280_SLAVE_UFS_MEM_CFG 98
#define SC7280_SLAVE_USB2 99
#define SC7280_SLAVE_USB3_0 100
#define SC7280_SLAVE_VENUS_CFG 101
#define SC7280_SLAVE_VSENSE_CTRL_CFG 102
#define SC7280_SLAVE_A1NOC_CFG 103
#define SC7280_SLAVE_A1NOC_SNOC 104
#define SC7280_SLAVE_A2NOC_CFG 105
#define SC7280_SLAVE_A2NOC_SNOC 106
#define SC7280_SLAVE_CNOC2_CNOC3 107
#define SC7280_SLAVE_CNOC3_CNOC2 108
#define SC7280_SLAVE_CNOC_A2NOC 109
#define SC7280_SLAVE_DDRSS_CFG 110
#define SC7280_SLAVE_GEM_NOC_CNOC 111
#define SC7280_SLAVE_GEM_NOC_CFG 112
#define SC7280_SLAVE_SNOC_GEM_NOC_GC 113
#define SC7280_SLAVE_SNOC_GEM_NOC_SF 114
#define SC7280_SLAVE_LLCC 115
#define SC7280_SLAVE_MNOC_HF_MEM_NOC 116
#define SC7280_SLAVE_MNOC_SF_MEM_NOC 117
#define SC7280_SLAVE_CNOC_MNOC_CFG 118
#define SC7280_SLAVE_CDSP_MEM_NOC 119
#define SC7280_SLAVE_MEM_NOC_PCIE_SNOC 120
#define SC7280_SLAVE_ANOC_PCIE_GEM_NOC 121
#define SC7280_SLAVE_SNOC_CFG 122
#define SC7280_SLAVE_QUP_CORE_0 123
#define SC7280_SLAVE_QUP_CORE_1 124
#define SC7280_SLAVE_BOOT_IMEM 125
#define SC7280_SLAVE_IMEM 126
#define SC7280_SLAVE_PIMEM 127
#define SC7280_SLAVE_SERVICE_NSP_NOC 128
#define SC7280_SLAVE_SERVICE_A1NOC 129
#define SC7280_SLAVE_SERVICE_A2NOC 130
#define SC7280_SLAVE_SERVICE_GEM_NOC_1 131
#define SC7280_SLAVE_SERVICE_MNOC 132
#define SC7280_SLAVE_SERVICES_LPASS_AML_NOC 133
#define SC7280_SLAVE_SERVICE_LPASS_AG_NOC 134
#define SC7280_SLAVE_SERVICE_GEM_NOC_2 135
#define SC7280_SLAVE_SERVICE_SNOC 136
#define SC7280_SLAVE_SERVICE_GEM_NOC 137
#define SC7280_SLAVE_PCIE_0 138
#define SC7280_SLAVE_PCIE_1 139
#define SC7280_SLAVE_QDSS_STM 140
#define SC7280_SLAVE_TCU 141
#endif

648
drivers/interconnect/qcom/sc8180x.c
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drivers/interconnect/qcom/sc8180x.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm #define SC8180X interconnect IDs
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8180X_H
#define __DRIVERS_INTERCONNECT_QCOM_SC8180X_H
#define SC8180X_MASTER_A1NOC_CFG 1
#define SC8180X_MASTER_UFS_CARD 2
#define SC8180X_MASTER_UFS_GEN4 3
#define SC8180X_MASTER_UFS_MEM 4
#define SC8180X_MASTER_USB3 5
#define SC8180X_MASTER_USB3_1 6
#define SC8180X_MASTER_USB3_2 7
#define SC8180X_MASTER_A2NOC_CFG 8
#define SC8180X_MASTER_QDSS_BAM 9
#define SC8180X_MASTER_QSPI_0 10
#define SC8180X_MASTER_QSPI_1 11
#define SC8180X_MASTER_QUP_0 12
#define SC8180X_MASTER_QUP_1 13
#define SC8180X_MASTER_QUP_2 14
#define SC8180X_MASTER_SENSORS_AHB 15
#define SC8180X_MASTER_CRYPTO_CORE_0 16
#define SC8180X_MASTER_IPA 17
#define SC8180X_MASTER_EMAC 18
#define SC8180X_MASTER_PCIE 19
#define SC8180X_MASTER_PCIE_1 20
#define SC8180X_MASTER_PCIE_2 21
#define SC8180X_MASTER_PCIE_3 22
#define SC8180X_MASTER_QDSS_ETR 23
#define SC8180X_MASTER_SDCC_2 24
#define SC8180X_MASTER_SDCC_4 25
#define SC8180X_MASTER_CAMNOC_HF0_UNCOMP 26
#define SC8180X_MASTER_CAMNOC_HF1_UNCOMP 27
#define SC8180X_MASTER_CAMNOC_SF_UNCOMP 28
#define SC8180X_MASTER_NPU 29
#define SC8180X_SNOC_CNOC_MAS 30
#define SC8180X_MASTER_CNOC_DC_NOC 31
#define SC8180X_MASTER_AMPSS_M0 32
#define SC8180X_MASTER_GPU_TCU 33
#define SC8180X_MASTER_SYS_TCU 34
#define SC8180X_MASTER_GEM_NOC_CFG 35
#define SC8180X_MASTER_COMPUTE_NOC 36
#define SC8180X_MASTER_GRAPHICS_3D 37
#define SC8180X_MASTER_MNOC_HF_MEM_NOC 38
#define SC8180X_MASTER_MNOC_SF_MEM_NOC 39
#define SC8180X_MASTER_GEM_NOC_PCIE_SNOC 40
#define SC8180X_MASTER_SNOC_GC_MEM_NOC 41
#define SC8180X_MASTER_SNOC_SF_MEM_NOC 42
#define SC8180X_MASTER_ECC 43
/* 44 was used by MASTER_IPA_CORE, now represented as RPMh clock */
#define SC8180X_MASTER_LLCC 45
#define SC8180X_MASTER_CNOC_MNOC_CFG 46
#define SC8180X_MASTER_CAMNOC_HF0 47
#define SC8180X_MASTER_CAMNOC_HF1 48
#define SC8180X_MASTER_CAMNOC_SF 49
#define SC8180X_MASTER_MDP_PORT0 50
#define SC8180X_MASTER_MDP_PORT1 51
#define SC8180X_MASTER_ROTATOR 52
#define SC8180X_MASTER_VIDEO_P0 53
#define SC8180X_MASTER_VIDEO_P1 54
#define SC8180X_MASTER_VIDEO_PROC 55
#define SC8180X_MASTER_SNOC_CFG 56
#define SC8180X_A1NOC_SNOC_MAS 57
#define SC8180X_A2NOC_SNOC_MAS 58
#define SC8180X_MASTER_GEM_NOC_SNOC 59
#define SC8180X_MASTER_PIMEM 60
#define SC8180X_MASTER_GIC 61
#define SC8180X_MASTER_MNOC_HF_MEM_NOC_DISPLAY 62
#define SC8180X_MASTER_MNOC_SF_MEM_NOC_DISPLAY 63
#define SC8180X_MASTER_LLCC_DISPLAY 64
#define SC8180X_MASTER_MDP_PORT0_DISPLAY 65
#define SC8180X_MASTER_MDP_PORT1_DISPLAY 66
#define SC8180X_MASTER_ROTATOR_DISPLAY 67
#define SC8180X_A1NOC_SNOC_SLV 68
#define SC8180X_SLAVE_SERVICE_A1NOC 69
#define SC8180X_A2NOC_SNOC_SLV 70
#define SC8180X_SLAVE_ANOC_PCIE_GEM_NOC 71
#define SC8180X_SLAVE_SERVICE_A2NOC 72
#define SC8180X_SLAVE_CAMNOC_UNCOMP 73
#define SC8180X_SLAVE_CDSP_MEM_NOC 74
#define SC8180X_SLAVE_A1NOC_CFG 75
#define SC8180X_SLAVE_A2NOC_CFG 76
#define SC8180X_SLAVE_AHB2PHY_CENTER 77
#define SC8180X_SLAVE_AHB2PHY_EAST 78
#define SC8180X_SLAVE_AHB2PHY_WEST 79
#define SC8180X_SLAVE_AHB2PHY_SOUTH 80
#define SC8180X_SLAVE_AOP 81
#define SC8180X_SLAVE_AOSS 82
#define SC8180X_SLAVE_CAMERA_CFG 83
#define SC8180X_SLAVE_CLK_CTL 84
#define SC8180X_SLAVE_CDSP_CFG 85
#define SC8180X_SLAVE_RBCPR_CX_CFG 86
#define SC8180X_SLAVE_RBCPR_MMCX_CFG 87
#define SC8180X_SLAVE_RBCPR_MX_CFG 88
#define SC8180X_SLAVE_CRYPTO_0_CFG 89
#define SC8180X_SLAVE_CNOC_DDRSS 90
#define SC8180X_SLAVE_DISPLAY_CFG 91
#define SC8180X_SLAVE_EMAC_CFG 92
#define SC8180X_SLAVE_GLM 93
#define SC8180X_SLAVE_GRAPHICS_3D_CFG 94
#define SC8180X_SLAVE_IMEM_CFG 95
#define SC8180X_SLAVE_IPA_CFG 96
#define SC8180X_SLAVE_CNOC_MNOC_CFG 97
#define SC8180X_SLAVE_NPU_CFG 98
#define SC8180X_SLAVE_PCIE_0_CFG 99
#define SC8180X_SLAVE_PCIE_1_CFG 100
#define SC8180X_SLAVE_PCIE_2_CFG 101
#define SC8180X_SLAVE_PCIE_3_CFG 102
#define SC8180X_SLAVE_PDM 103
#define SC8180X_SLAVE_PIMEM_CFG 104
#define SC8180X_SLAVE_PRNG 105
#define SC8180X_SLAVE_QDSS_CFG 106
#define SC8180X_SLAVE_QSPI_0 107
#define SC8180X_SLAVE_QSPI_1 108
#define SC8180X_SLAVE_QUP_1 109
#define SC8180X_SLAVE_QUP_2 110
#define SC8180X_SLAVE_QUP_0 111
#define SC8180X_SLAVE_SDCC_2 112
#define SC8180X_SLAVE_SDCC_4 113
#define SC8180X_SLAVE_SECURITY 114
#define SC8180X_SLAVE_SNOC_CFG 115
#define SC8180X_SLAVE_SPSS_CFG 116
#define SC8180X_SLAVE_TCSR 117
#define SC8180X_SLAVE_TLMM_EAST 118
#define SC8180X_SLAVE_TLMM_SOUTH 119
#define SC8180X_SLAVE_TLMM_WEST 120
#define SC8180X_SLAVE_TSIF 121
#define SC8180X_SLAVE_UFS_CARD_CFG 122
#define SC8180X_SLAVE_UFS_MEM_0_CFG 123
#define SC8180X_SLAVE_UFS_MEM_1_CFG 124
#define SC8180X_SLAVE_USB3 125
#define SC8180X_SLAVE_USB3_1 126
#define SC8180X_SLAVE_USB3_2 127
#define SC8180X_SLAVE_VENUS_CFG 128
#define SC8180X_SLAVE_VSENSE_CTRL_CFG 129
#define SC8180X_SLAVE_SERVICE_CNOC 130
#define SC8180X_SLAVE_GEM_NOC_CFG 131
#define SC8180X_SLAVE_LLCC_CFG 132
#define SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG 133
#define SC8180X_SLAVE_ECC 134
#define SC8180X_SLAVE_GEM_NOC_SNOC 135
#define SC8180X_SLAVE_LLCC 136
#define SC8180X_SLAVE_SERVICE_GEM_NOC 137
#define SC8180X_SLAVE_SERVICE_GEM_NOC_1 138
/* 139 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SC8180X_SLAVE_EBI_CH0 140
#define SC8180X_SLAVE_MNOC_SF_MEM_NOC 141
#define SC8180X_SLAVE_MNOC_HF_MEM_NOC 142
#define SC8180X_SLAVE_SERVICE_MNOC 143
#define SC8180X_SLAVE_APPSS 144
#define SC8180X_SNOC_CNOC_SLV 145
#define SC8180X_SLAVE_SNOC_GEM_NOC_GC 146
#define SC8180X_SLAVE_SNOC_GEM_NOC_SF 147
#define SC8180X_SLAVE_OCIMEM 148
#define SC8180X_SLAVE_PIMEM 149
#define SC8180X_SLAVE_SERVICE_SNOC 150
#define SC8180X_SLAVE_PCIE_0 151
#define SC8180X_SLAVE_PCIE_1 152
#define SC8180X_SLAVE_PCIE_2 153
#define SC8180X_SLAVE_PCIE_3 154
#define SC8180X_SLAVE_QDSS_STM 155
#define SC8180X_SLAVE_TCU 156
#define SC8180X_SLAVE_LLCC_DISPLAY 157
#define SC8180X_SLAVE_EBI_CH0_DISPLAY 158
#define SC8180X_SLAVE_MNOC_SF_MEM_NOC_DISPLAY 159
#define SC8180X_SLAVE_MNOC_HF_MEM_NOC_DISPLAY 160
#define SC8180X_MASTER_QUP_CORE_0 163
#define SC8180X_MASTER_QUP_CORE_1 164
#define SC8180X_MASTER_QUP_CORE_2 165
#define SC8180X_SLAVE_QUP_CORE_0 166
#define SC8180X_SLAVE_QUP_CORE_1 167
#define SC8180X_SLAVE_QUP_CORE_2 168
#endif

825
drivers/interconnect/qcom/sc8280xp.c
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drivers/interconnect/qcom/sc8280xp.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H
#define __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H
#define SC8280XP_MASTER_GPU_TCU 0
#define SC8280XP_MASTER_PCIE_TCU 1
#define SC8280XP_MASTER_SYS_TCU 2
#define SC8280XP_MASTER_APPSS_PROC 3
/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SC8280XP_MASTER_LLCC 5
#define SC8280XP_MASTER_CNOC_LPASS_AG_NOC 6
#define SC8280XP_MASTER_CDSP_NOC_CFG 7
#define SC8280XP_MASTER_CDSPB_NOC_CFG 8
#define SC8280XP_MASTER_QDSS_BAM 9
#define SC8280XP_MASTER_QSPI_0 10
#define SC8280XP_MASTER_QUP_0 11
#define SC8280XP_MASTER_QUP_1 12
#define SC8280XP_MASTER_QUP_2 13
#define SC8280XP_MASTER_A1NOC_CFG 14
#define SC8280XP_MASTER_A2NOC_CFG 15
#define SC8280XP_MASTER_A1NOC_SNOC 16
#define SC8280XP_MASTER_A2NOC_SNOC 17
#define SC8280XP_MASTER_USB_NOC_SNOC 18
#define SC8280XP_MASTER_CAMNOC_HF 19
#define SC8280XP_MASTER_COMPUTE_NOC 20
#define SC8280XP_MASTER_COMPUTE_NOC_1 21
#define SC8280XP_MASTER_CNOC_DC_NOC 22
#define SC8280XP_MASTER_GEM_NOC_CFG 23
#define SC8280XP_MASTER_GEM_NOC_CNOC 24
#define SC8280XP_MASTER_GEM_NOC_PCIE_SNOC 25
#define SC8280XP_MASTER_GFX3D 26
#define SC8280XP_MASTER_LPASS_ANOC 27
#define SC8280XP_MASTER_MDP0 28
#define SC8280XP_MASTER_MDP1 29
#define SC8280XP_MASTER_MDP_CORE1_0 30
#define SC8280XP_MASTER_MDP_CORE1_1 31
#define SC8280XP_MASTER_CNOC_MNOC_CFG 32
#define SC8280XP_MASTER_MNOC_HF_MEM_NOC 33
#define SC8280XP_MASTER_MNOC_SF_MEM_NOC 34
#define SC8280XP_MASTER_ANOC_PCIE_GEM_NOC 35
#define SC8280XP_MASTER_ROTATOR 36
#define SC8280XP_MASTER_ROTATOR_1 37
#define SC8280XP_MASTER_SNOC_CFG 38
#define SC8280XP_MASTER_SNOC_GC_MEM_NOC 39
#define SC8280XP_MASTER_SNOC_SF_MEM_NOC 40
#define SC8280XP_MASTER_VIDEO_P0 41
#define SC8280XP_MASTER_VIDEO_P1 42
#define SC8280XP_MASTER_VIDEO_PROC 43
#define SC8280XP_MASTER_QUP_CORE_0 44
#define SC8280XP_MASTER_QUP_CORE_1 45
#define SC8280XP_MASTER_QUP_CORE_2 46
#define SC8280XP_MASTER_CAMNOC_ICP 47
#define SC8280XP_MASTER_CAMNOC_SF 48
#define SC8280XP_MASTER_CRYPTO 49
#define SC8280XP_MASTER_IPA 50
#define SC8280XP_MASTER_LPASS_PROC 51
#define SC8280XP_MASTER_CDSP_PROC 52
#define SC8280XP_MASTER_CDSP_PROC_B 53
#define SC8280XP_MASTER_PIMEM 54
#define SC8280XP_MASTER_SENSORS_PROC 55
#define SC8280XP_MASTER_SP 56
#define SC8280XP_MASTER_EMAC 57
#define SC8280XP_MASTER_EMAC_1 58
#define SC8280XP_MASTER_GIC 59
#define SC8280XP_MASTER_PCIE_0 60
#define SC8280XP_MASTER_PCIE_1 61
#define SC8280XP_MASTER_PCIE_2A 62
#define SC8280XP_MASTER_PCIE_2B 63
#define SC8280XP_MASTER_PCIE_3A 64
#define SC8280XP_MASTER_PCIE_3B 65
#define SC8280XP_MASTER_PCIE_4 66
#define SC8280XP_MASTER_QDSS_ETR 67
#define SC8280XP_MASTER_SDCC_2 68
#define SC8280XP_MASTER_SDCC_4 69
#define SC8280XP_MASTER_UFS_CARD 70
#define SC8280XP_MASTER_UFS_MEM 71
#define SC8280XP_MASTER_USB3_0 72
#define SC8280XP_MASTER_USB3_1 73
#define SC8280XP_MASTER_USB3_MP 74
#define SC8280XP_MASTER_USB4_0 75
#define SC8280XP_MASTER_USB4_1 76
#define SC8280XP_SLAVE_EBI1 512
/* 513 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SC8280XP_SLAVE_AHB2PHY_0 514
#define SC8280XP_SLAVE_AHB2PHY_1 515
#define SC8280XP_SLAVE_AHB2PHY_2 516
#define SC8280XP_SLAVE_AOSS 517
#define SC8280XP_SLAVE_APPSS 518
#define SC8280XP_SLAVE_CAMERA_CFG 519
#define SC8280XP_SLAVE_CLK_CTL 520
#define SC8280XP_SLAVE_CDSP_CFG 521
#define SC8280XP_SLAVE_CDSP1_CFG 522
#define SC8280XP_SLAVE_RBCPR_CX_CFG 523
#define SC8280XP_SLAVE_RBCPR_MMCX_CFG 524
#define SC8280XP_SLAVE_RBCPR_MX_CFG 525
#define SC8280XP_SLAVE_CPR_NSPCX 526
#define SC8280XP_SLAVE_CRYPTO_0_CFG 527
#define SC8280XP_SLAVE_CX_RDPM 528
#define SC8280XP_SLAVE_DCC_CFG 529
#define SC8280XP_SLAVE_DISPLAY_CFG 530
#define SC8280XP_SLAVE_DISPLAY1_CFG 531
#define SC8280XP_SLAVE_EMAC_CFG 532
#define SC8280XP_SLAVE_EMAC1_CFG 533
#define SC8280XP_SLAVE_GFX3D_CFG 534
#define SC8280XP_SLAVE_HWKM 535
#define SC8280XP_SLAVE_IMEM_CFG 536
#define SC8280XP_SLAVE_IPA_CFG 537
#define SC8280XP_SLAVE_IPC_ROUTER_CFG 538
#define SC8280XP_SLAVE_LLCC_CFG 539
#define SC8280XP_SLAVE_LPASS 540
#define SC8280XP_SLAVE_LPASS_CORE_CFG 541
#define SC8280XP_SLAVE_LPASS_LPI_CFG 542
#define SC8280XP_SLAVE_LPASS_MPU_CFG 543
#define SC8280XP_SLAVE_LPASS_TOP_CFG 544
#define SC8280XP_SLAVE_MX_RDPM 545
#define SC8280XP_SLAVE_MXC_RDPM 546
#define SC8280XP_SLAVE_PCIE_0_CFG 547
#define SC8280XP_SLAVE_PCIE_1_CFG 548
#define SC8280XP_SLAVE_PCIE_2A_CFG 549
#define SC8280XP_SLAVE_PCIE_2B_CFG 550
#define SC8280XP_SLAVE_PCIE_3A_CFG 551
#define SC8280XP_SLAVE_PCIE_3B_CFG 552
#define SC8280XP_SLAVE_PCIE_4_CFG 553
#define SC8280XP_SLAVE_PCIE_RSC_CFG 554
#define SC8280XP_SLAVE_PDM 555
#define SC8280XP_SLAVE_PIMEM_CFG 556
#define SC8280XP_SLAVE_PKA_WRAPPER_CFG 557
#define SC8280XP_SLAVE_PMU_WRAPPER_CFG 558
#define SC8280XP_SLAVE_QDSS_CFG 559
#define SC8280XP_SLAVE_QSPI_0 560
#define SC8280XP_SLAVE_QUP_0 561
#define SC8280XP_SLAVE_QUP_1 562
#define SC8280XP_SLAVE_QUP_2 563
#define SC8280XP_SLAVE_SDCC_2 564
#define SC8280XP_SLAVE_SDCC_4 565
#define SC8280XP_SLAVE_SECURITY 566
#define SC8280XP_SLAVE_SMMUV3_CFG 567
#define SC8280XP_SLAVE_SMSS_CFG 568
#define SC8280XP_SLAVE_SPSS_CFG 569
#define SC8280XP_SLAVE_TCSR 570
#define SC8280XP_SLAVE_TLMM 571
#define SC8280XP_SLAVE_UFS_CARD_CFG 572
#define SC8280XP_SLAVE_UFS_MEM_CFG 573
#define SC8280XP_SLAVE_USB3_0 574
#define SC8280XP_SLAVE_USB3_1 575
#define SC8280XP_SLAVE_USB3_MP 576
#define SC8280XP_SLAVE_USB4_0 577
#define SC8280XP_SLAVE_USB4_1 578
#define SC8280XP_SLAVE_VENUS_CFG 579
#define SC8280XP_SLAVE_VSENSE_CTRL_CFG 580
#define SC8280XP_SLAVE_VSENSE_CTRL_R_CFG 581
#define SC8280XP_SLAVE_A1NOC_CFG 582
#define SC8280XP_SLAVE_A1NOC_SNOC 583
#define SC8280XP_SLAVE_A2NOC_CFG 584
#define SC8280XP_SLAVE_A2NOC_SNOC 585
#define SC8280XP_SLAVE_USB_NOC_SNOC 586
#define SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG 587
#define SC8280XP_SLAVE_DDRSS_CFG 588
#define SC8280XP_SLAVE_GEM_NOC_CNOC 589
#define SC8280XP_SLAVE_GEM_NOC_CFG 590
#define SC8280XP_SLAVE_SNOC_GEM_NOC_GC 591
#define SC8280XP_SLAVE_SNOC_GEM_NOC_SF 592
#define SC8280XP_SLAVE_LLCC 593
#define SC8280XP_SLAVE_MNOC_HF_MEM_NOC 594
#define SC8280XP_SLAVE_MNOC_SF_MEM_NOC 595
#define SC8280XP_SLAVE_CNOC_MNOC_CFG 596
#define SC8280XP_SLAVE_CDSP_MEM_NOC 597
#define SC8280XP_SLAVE_CDSPB_MEM_NOC 598
#define SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC 599
#define SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC 600
#define SC8280XP_SLAVE_SNOC_CFG 601
#define SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG 602
#define SC8280XP_SLAVE_LPASS_SNOC 603
#define SC8280XP_SLAVE_QUP_CORE_0 604
#define SC8280XP_SLAVE_QUP_CORE_1 605
#define SC8280XP_SLAVE_QUP_CORE_2 606
#define SC8280XP_SLAVE_IMEM 607
#define SC8280XP_SLAVE_NSP_XFR 608
#define SC8280XP_SLAVE_NSPB_XFR 609
#define SC8280XP_SLAVE_PIMEM 610
#define SC8280XP_SLAVE_SERVICE_NSP_NOC 611
#define SC8280XP_SLAVE_SERVICE_NSPB_NOC 612
#define SC8280XP_SLAVE_SERVICE_A1NOC 613
#define SC8280XP_SLAVE_SERVICE_A2NOC 614
#define SC8280XP_SLAVE_SERVICE_CNOC 615
#define SC8280XP_SLAVE_SERVICE_GEM_NOC_1 616
#define SC8280XP_SLAVE_SERVICE_MNOC 617
#define SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC 618
#define SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC 619
#define SC8280XP_SLAVE_SERVICE_GEM_NOC_2 620
#define SC8280XP_SLAVE_SERVICE_SNOC 621
#define SC8280XP_SLAVE_SERVICE_GEM_NOC 622
#define SC8280XP_SLAVE_PCIE_0 623
#define SC8280XP_SLAVE_PCIE_1 624
#define SC8280XP_SLAVE_PCIE_2A 625
#define SC8280XP_SLAVE_PCIE_2B 626
#define SC8280XP_SLAVE_PCIE_3A 627
#define SC8280XP_SLAVE_PCIE_3B 628
#define SC8280XP_SLAVE_PCIE_4 629
#define SC8280XP_SLAVE_QDSS_STM 630
#define SC8280XP_SLAVE_SMSS 631
#define SC8280XP_SLAVE_TCU 632
#endif

522
drivers/interconnect/qcom/sdm670.c
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drivers/interconnect/qcom/sdm670.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm #define SDM670 interconnect IDs
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM670_H
#define __DRIVERS_INTERCONNECT_QCOM_SDM670_H
#define SDM670_MASTER_A1NOC_CFG 0
#define SDM670_MASTER_A1NOC_SNOC 1
#define SDM670_MASTER_A2NOC_CFG 2
#define SDM670_MASTER_A2NOC_SNOC 3
#define SDM670_MASTER_AMPSS_M0 4
#define SDM670_MASTER_BLSP_1 5
#define SDM670_MASTER_BLSP_2 6
#define SDM670_MASTER_CAMNOC_HF0 7
#define SDM670_MASTER_CAMNOC_HF0_UNCOMP 8
#define SDM670_MASTER_CAMNOC_HF1 9
#define SDM670_MASTER_CAMNOC_HF1_UNCOMP 10
#define SDM670_MASTER_CAMNOC_SF 11
#define SDM670_MASTER_CAMNOC_SF_UNCOMP 12
#define SDM670_MASTER_CNOC_A2NOC 13
#define SDM670_MASTER_CNOC_DC_NOC 14
#define SDM670_MASTER_CNOC_MNOC_CFG 15
#define SDM670_MASTER_CRYPTO_CORE_0 16
#define SDM670_MASTER_EMMC 17
#define SDM670_MASTER_GIC 18
#define SDM670_MASTER_GNOC_CFG 19
#define SDM670_MASTER_GNOC_MEM_NOC 20
#define SDM670_MASTER_GNOC_SNOC 21
#define SDM670_MASTER_GRAPHICS_3D 22
#define SDM670_MASTER_IPA 23
#define SDM670_MASTER_LLCC 24
#define SDM670_MASTER_MDP_PORT0 25
#define SDM670_MASTER_MDP_PORT1 26
#define SDM670_MASTER_MEM_NOC_CFG 27
#define SDM670_MASTER_MEM_NOC_SNOC 28
#define SDM670_MASTER_MNOC_HF_MEM_NOC 29
#define SDM670_MASTER_MNOC_SF_MEM_NOC 30
#define SDM670_MASTER_PIMEM 31
#define SDM670_MASTER_QDSS_BAM 32
#define SDM670_MASTER_QDSS_ETR 33
#define SDM670_MASTER_ROTATOR 34
#define SDM670_MASTER_SDCC_2 35
#define SDM670_MASTER_SDCC_4 36
#define SDM670_MASTER_SNOC_CFG 37
#define SDM670_MASTER_SNOC_CNOC 38
#define SDM670_MASTER_SNOC_GC_MEM_NOC 39
#define SDM670_MASTER_SNOC_SF_MEM_NOC 40
#define SDM670_MASTER_SPDM 41
#define SDM670_MASTER_TCU_0 42
#define SDM670_MASTER_TSIF 43
#define SDM670_MASTER_UFS_MEM 44
#define SDM670_MASTER_USB3 45
#define SDM670_MASTER_VIDEO_P0 46
#define SDM670_MASTER_VIDEO_P1 47
#define SDM670_MASTER_VIDEO_PROC 48
#define SDM670_SLAVE_A1NOC_CFG 49
#define SDM670_SLAVE_A1NOC_SNOC 50
#define SDM670_SLAVE_A2NOC_CFG 51
#define SDM670_SLAVE_A2NOC_SNOC 52
#define SDM670_SLAVE_AOP 53
#define SDM670_SLAVE_AOSS 54
#define SDM670_SLAVE_APPSS 55
#define SDM670_SLAVE_BLSP_1 56
#define SDM670_SLAVE_BLSP_2 57
#define SDM670_SLAVE_CAMERA_CFG 58
#define SDM670_SLAVE_CAMNOC_UNCOMP 59
#define SDM670_SLAVE_CDSP_CFG 60
#define SDM670_SLAVE_CLK_CTL 61
#define SDM670_SLAVE_CNOC_A2NOC 62
#define SDM670_SLAVE_CNOC_DDRSS 63
#define SDM670_SLAVE_CNOC_MNOC_CFG 64
#define SDM670_SLAVE_CRYPTO_0_CFG 65
#define SDM670_SLAVE_DCC_CFG 66
#define SDM670_SLAVE_DISPLAY_CFG 67
#define SDM670_SLAVE_EBI_CH0 68
#define SDM670_SLAVE_EMMC_CFG 69
#define SDM670_SLAVE_GLM 70
#define SDM670_SLAVE_GNOC_MEM_NOC 71
#define SDM670_SLAVE_GNOC_SNOC 72
#define SDM670_SLAVE_GRAPHICS_3D_CFG 73
#define SDM670_SLAVE_IMEM_CFG 74
#define SDM670_SLAVE_IPA_CFG 75
#define SDM670_SLAVE_LLCC 76
#define SDM670_SLAVE_LLCC_CFG 77
#define SDM670_SLAVE_MEM_NOC_CFG 78
#define SDM670_SLAVE_MEM_NOC_GNOC 79
#define SDM670_SLAVE_MEM_NOC_SNOC 80
#define SDM670_SLAVE_MNOC_HF_MEM_NOC 81
#define SDM670_SLAVE_MNOC_SF_MEM_NOC 82
#define SDM670_SLAVE_MSS_PROC_MS_MPU_CFG 83
#define SDM670_SLAVE_OCIMEM 84
#define SDM670_SLAVE_PDM 85
#define SDM670_SLAVE_PIMEM 86
#define SDM670_SLAVE_PIMEM_CFG 87
#define SDM670_SLAVE_PRNG 88
#define SDM670_SLAVE_QDSS_CFG 89
#define SDM670_SLAVE_QDSS_STM 90
#define SDM670_SLAVE_RBCPR_CX_CFG 91
#define SDM670_SLAVE_SDCC_2 92
#define SDM670_SLAVE_SDCC_4 93
#define SDM670_SLAVE_SERVICE_A1NOC 94
#define SDM670_SLAVE_SERVICE_A2NOC 95
#define SDM670_SLAVE_SERVICE_CNOC 96
#define SDM670_SLAVE_SERVICE_GNOC 97
#define SDM670_SLAVE_SERVICE_MEM_NOC 98
#define SDM670_SLAVE_SERVICE_MNOC 99
#define SDM670_SLAVE_SERVICE_SNOC 100
#define SDM670_SLAVE_SNOC_CFG 101
#define SDM670_SLAVE_SNOC_CNOC 102
#define SDM670_SLAVE_SNOC_MEM_NOC_GC 103
#define SDM670_SLAVE_SNOC_MEM_NOC_SF 104
#define SDM670_SLAVE_SOUTH_PHY_CFG 105
#define SDM670_SLAVE_SPDM_WRAPPER 106
#define SDM670_SLAVE_TCSR 107
#define SDM670_SLAVE_TCU 108
#define SDM670_SLAVE_TLMM_NORTH 109
#define SDM670_SLAVE_TLMM_SOUTH 110
#define SDM670_SLAVE_TSIF 111
#define SDM670_SLAVE_UFS_MEM_CFG 112
#define SDM670_SLAVE_USB3 113
#define SDM670_SLAVE_VENUS_CFG 114
#define SDM670_SLAVE_VSENSE_CTRL_CFG 115
#endif

766
drivers/interconnect/qcom/sdm845.c
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File diff suppressed because it is too large Load Diff

140
drivers/interconnect/qcom/sdm845.h
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@@ -1,140 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
#define __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
#define SDM845_MASTER_A1NOC_CFG 1
#define SDM845_MASTER_BLSP_1 2
#define SDM845_MASTER_TSIF 3
#define SDM845_MASTER_SDCC_2 4
#define SDM845_MASTER_SDCC_4 5
#define SDM845_MASTER_UFS_CARD 6
#define SDM845_MASTER_UFS_MEM 7
#define SDM845_MASTER_PCIE_0 8
#define SDM845_MASTER_A2NOC_CFG 9
#define SDM845_MASTER_QDSS_BAM 10
#define SDM845_MASTER_BLSP_2 11
#define SDM845_MASTER_CNOC_A2NOC 12
#define SDM845_MASTER_CRYPTO 13
#define SDM845_MASTER_IPA 14
#define SDM845_MASTER_PCIE_1 15
#define SDM845_MASTER_QDSS_ETR 16
#define SDM845_MASTER_USB3_0 17
#define SDM845_MASTER_USB3_1 18
#define SDM845_MASTER_CAMNOC_HF0_UNCOMP 19
#define SDM845_MASTER_CAMNOC_HF1_UNCOMP 20
#define SDM845_MASTER_CAMNOC_SF_UNCOMP 21
#define SDM845_MASTER_SPDM 22
#define SDM845_MASTER_TIC 23
#define SDM845_MASTER_SNOC_CNOC 24
#define SDM845_MASTER_QDSS_DAP 25
#define SDM845_MASTER_CNOC_DC_NOC 26
#define SDM845_MASTER_APPSS_PROC 27
#define SDM845_MASTER_GNOC_CFG 28
#define SDM845_MASTER_LLCC 29
#define SDM845_MASTER_TCU_0 30
#define SDM845_MASTER_MEM_NOC_CFG 31
#define SDM845_MASTER_GNOC_MEM_NOC 32
#define SDM845_MASTER_MNOC_HF_MEM_NOC 33
#define SDM845_MASTER_MNOC_SF_MEM_NOC 34
#define SDM845_MASTER_SNOC_GC_MEM_NOC 35
#define SDM845_MASTER_SNOC_SF_MEM_NOC 36
#define SDM845_MASTER_GFX3D 37
#define SDM845_MASTER_CNOC_MNOC_CFG 38
#define SDM845_MASTER_CAMNOC_HF0 39
#define SDM845_MASTER_CAMNOC_HF1 40
#define SDM845_MASTER_CAMNOC_SF 41
#define SDM845_MASTER_MDP0 42
#define SDM845_MASTER_MDP1 43
#define SDM845_MASTER_ROTATOR 44
#define SDM845_MASTER_VIDEO_P0 45
#define SDM845_MASTER_VIDEO_P1 46
#define SDM845_MASTER_VIDEO_PROC 47
#define SDM845_MASTER_SNOC_CFG 48
#define SDM845_MASTER_A1NOC_SNOC 49
#define SDM845_MASTER_A2NOC_SNOC 50
#define SDM845_MASTER_GNOC_SNOC 51
#define SDM845_MASTER_MEM_NOC_SNOC 52
#define SDM845_MASTER_ANOC_PCIE_SNOC 53
#define SDM845_MASTER_PIMEM 54
#define SDM845_MASTER_GIC 55
#define SDM845_SLAVE_A1NOC_SNOC 56
#define SDM845_SLAVE_SERVICE_A1NOC 57
#define SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC 58
#define SDM845_SLAVE_A2NOC_SNOC 59
#define SDM845_SLAVE_ANOC_PCIE_SNOC 60
#define SDM845_SLAVE_SERVICE_A2NOC 61
#define SDM845_SLAVE_CAMNOC_UNCOMP 62
#define SDM845_SLAVE_A1NOC_CFG 63
#define SDM845_SLAVE_A2NOC_CFG 64
#define SDM845_SLAVE_AOP 65
#define SDM845_SLAVE_AOSS 66
#define SDM845_SLAVE_CAMERA_CFG 67
#define SDM845_SLAVE_CLK_CTL 68
#define SDM845_SLAVE_CDSP_CFG 69
#define SDM845_SLAVE_RBCPR_CX_CFG 70
#define SDM845_SLAVE_CRYPTO_0_CFG 71
#define SDM845_SLAVE_DCC_CFG 72
#define SDM845_SLAVE_CNOC_DDRSS 73
#define SDM845_SLAVE_DISPLAY_CFG 74
#define SDM845_SLAVE_GLM 75
#define SDM845_SLAVE_GFX3D_CFG 76
#define SDM845_SLAVE_IMEM_CFG 77
#define SDM845_SLAVE_IPA_CFG 78
#define SDM845_SLAVE_CNOC_MNOC_CFG 79
#define SDM845_SLAVE_PCIE_0_CFG 80
#define SDM845_SLAVE_PCIE_1_CFG 81
#define SDM845_SLAVE_PDM 82
#define SDM845_SLAVE_SOUTH_PHY_CFG 83
#define SDM845_SLAVE_PIMEM_CFG 84
#define SDM845_SLAVE_PRNG 85
#define SDM845_SLAVE_QDSS_CFG 86
#define SDM845_SLAVE_BLSP_2 87
#define SDM845_SLAVE_BLSP_1 88
#define SDM845_SLAVE_SDCC_2 89
#define SDM845_SLAVE_SDCC_4 90
#define SDM845_SLAVE_SNOC_CFG 91
#define SDM845_SLAVE_SPDM_WRAPPER 92
#define SDM845_SLAVE_SPSS_CFG 93
#define SDM845_SLAVE_TCSR 94
#define SDM845_SLAVE_TLMM_NORTH 95
#define SDM845_SLAVE_TLMM_SOUTH 96
#define SDM845_SLAVE_TSIF 97
#define SDM845_SLAVE_UFS_CARD_CFG 98
#define SDM845_SLAVE_UFS_MEM_CFG 99
#define SDM845_SLAVE_USB3_0 100
#define SDM845_SLAVE_USB3_1 101
#define SDM845_SLAVE_VENUS_CFG 102
#define SDM845_SLAVE_VSENSE_CTRL_CFG 103
#define SDM845_SLAVE_CNOC_A2NOC 104
#define SDM845_SLAVE_SERVICE_CNOC 105
#define SDM845_SLAVE_LLCC_CFG 106
#define SDM845_SLAVE_MEM_NOC_CFG 107
#define SDM845_SLAVE_GNOC_SNOC 108
#define SDM845_SLAVE_GNOC_MEM_NOC 109
#define SDM845_SLAVE_SERVICE_GNOC 110
#define SDM845_SLAVE_EBI1 111
#define SDM845_SLAVE_MSS_PROC_MS_MPU_CFG 112
#define SDM845_SLAVE_MEM_NOC_GNOC 113
#define SDM845_SLAVE_LLCC 114
#define SDM845_SLAVE_MEM_NOC_SNOC 115
#define SDM845_SLAVE_SERVICE_MEM_NOC 116
#define SDM845_SLAVE_MNOC_SF_MEM_NOC 117
#define SDM845_SLAVE_MNOC_HF_MEM_NOC 118
#define SDM845_SLAVE_SERVICE_MNOC 119
#define SDM845_SLAVE_APPSS 120
#define SDM845_SLAVE_SNOC_CNOC 121
#define SDM845_SLAVE_SNOC_MEM_NOC_GC 122
#define SDM845_SLAVE_SNOC_MEM_NOC_SF 123
#define SDM845_SLAVE_IMEM 124
#define SDM845_SLAVE_PCIE_0 125
#define SDM845_SLAVE_PCIE_1 126
#define SDM845_SLAVE_PIMEM 127
#define SDM845_SLAVE_SERVICE_SNOC 128
#define SDM845_SLAVE_QDSS_STM 129
#define SDM845_SLAVE_TCU 130
#endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */

489
drivers/interconnect/qcom/sdx55.c
View File

@@ -17,628 +17,617 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
#include "sdx55.h"
static struct qcom_icc_node llcc_mc;
static struct qcom_icc_node acm_tcu;
static struct qcom_icc_node qnm_snoc_gc;
static struct qcom_icc_node xm_apps_rdwr;
static struct qcom_icc_node qhm_audio;
static struct qcom_icc_node qhm_blsp1;
static struct qcom_icc_node qhm_qdss_bam;
static struct qcom_icc_node qhm_qpic;
static struct qcom_icc_node qhm_snoc_cfg;
static struct qcom_icc_node qhm_spmi_fetcher1;
static struct qcom_icc_node qnm_aggre_noc;
static struct qcom_icc_node qnm_ipa;
static struct qcom_icc_node qnm_memnoc;
static struct qcom_icc_node qnm_memnoc_pcie;
static struct qcom_icc_node qxm_crypto;
static struct qcom_icc_node xm_emac;
static struct qcom_icc_node xm_ipa2pcie_slv;
static struct qcom_icc_node xm_pcie;
static struct qcom_icc_node xm_qdss_etr;
static struct qcom_icc_node xm_sdc1;
static struct qcom_icc_node xm_usb3;
static struct qcom_icc_node ebi;
static struct qcom_icc_node qns_llcc;
static struct qcom_icc_node qns_memnoc_snoc;
static struct qcom_icc_node qns_sys_pcie;
static struct qcom_icc_node qhs_aop;
static struct qcom_icc_node qhs_aoss;
static struct qcom_icc_node qhs_apss;
static struct qcom_icc_node qhs_audio;
static struct qcom_icc_node qhs_blsp1;
static struct qcom_icc_node qhs_clk_ctl;
static struct qcom_icc_node qhs_crypto0_cfg;
static struct qcom_icc_node qhs_ddrss_cfg;
static struct qcom_icc_node qhs_ecc_cfg;
static struct qcom_icc_node qhs_emac_cfg;
static struct qcom_icc_node qhs_imem_cfg;
static struct qcom_icc_node qhs_ipa;
static struct qcom_icc_node qhs_mss_cfg;
static struct qcom_icc_node qhs_pcie_parf;
static struct qcom_icc_node qhs_pdm;
static struct qcom_icc_node qhs_prng;
static struct qcom_icc_node qhs_qdss_cfg;
static struct qcom_icc_node qhs_qpic;
static struct qcom_icc_node qhs_sdc1;
static struct qcom_icc_node qhs_snoc_cfg;
static struct qcom_icc_node qhs_spmi_fetcher;
static struct qcom_icc_node qhs_spmi_vgi_coex;
static struct qcom_icc_node qhs_tcsr;
static struct qcom_icc_node qhs_tlmm;
static struct qcom_icc_node qhs_usb3;
static struct qcom_icc_node qhs_usb3_phy;
static struct qcom_icc_node qns_aggre_noc;
static struct qcom_icc_node qns_snoc_memnoc;
static struct qcom_icc_node qxs_imem;
static struct qcom_icc_node srvc_snoc;
static struct qcom_icc_node xs_pcie;
static struct qcom_icc_node xs_qdss_stm;
static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
.id = SDX55_MASTER_LLCC,
.channels = 4,
.buswidth = 4,
.num_links = 1,
.links = { SDX55_SLAVE_EBI_CH0 },
.link_nodes = { &ebi },
};
static struct qcom_icc_node acm_tcu = {
.name = "acm_tcu",
.id = SDX55_MASTER_TCU_0,
.channels = 1,
.buswidth = 8,
.num_links = 3,
.links = { SDX55_SLAVE_LLCC,
SDX55_SLAVE_MEM_NOC_SNOC,
SDX55_SLAVE_MEM_NOC_PCIE_SNOC
},
.link_nodes = { &qns_llcc,
&qns_memnoc_snoc,
&qns_sys_pcie },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
.id = SDX55_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_SLAVE_LLCC },
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_node xm_apps_rdwr = {
.name = "xm_apps_rdwr",
.id = SDX55_MASTER_AMPSS_M0,
.channels = 1,
.buswidth = 16,
.num_links = 3,
.links = { SDX55_SLAVE_LLCC,
SDX55_SLAVE_MEM_NOC_SNOC,
SDX55_SLAVE_MEM_NOC_PCIE_SNOC
},
.link_nodes = { &qns_llcc,
&qns_memnoc_snoc,
&qns_sys_pcie },
};
static struct qcom_icc_node qhm_audio = {
.name = "qhm_audio",
.id = SDX55_MASTER_AUDIO,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX55_SLAVE_ANOC_SNOC },
.link_nodes = { &qns_aggre_noc },
};
static struct qcom_icc_node qhm_blsp1 = {
.name = "qhm_blsp1",
.id = SDX55_MASTER_BLSP_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX55_SLAVE_ANOC_SNOC },
.link_nodes = { &qns_aggre_noc },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.id = SDX55_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.num_links = 28,
.links = { SDX55_SLAVE_SNOC_CFG,
SDX55_SLAVE_EMAC_CFG,
SDX55_SLAVE_USB3,
SDX55_SLAVE_TLMM,
SDX55_SLAVE_SPMI_FETCHER,
SDX55_SLAVE_QDSS_CFG,
SDX55_SLAVE_PDM,
SDX55_SLAVE_SNOC_MEM_NOC_GC,
SDX55_SLAVE_TCSR,
SDX55_SLAVE_CNOC_DDRSS,
SDX55_SLAVE_SPMI_VGI_COEX,
SDX55_SLAVE_QPIC,
SDX55_SLAVE_OCIMEM,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_USB3_PHY_CFG,
SDX55_SLAVE_AOP,
SDX55_SLAVE_BLSP_1,
SDX55_SLAVE_SDCC_1,
SDX55_SLAVE_CNOC_MSS,
SDX55_SLAVE_PCIE_PARF,
SDX55_SLAVE_ECC_CFG,
SDX55_SLAVE_AUDIO,
SDX55_SLAVE_AOSS,
SDX55_SLAVE_PRNG,
SDX55_SLAVE_CRYPTO_0_CFG,
SDX55_SLAVE_TCU,
SDX55_SLAVE_CLK_CTL,
SDX55_SLAVE_IMEM_CFG
},
.link_nodes = { &qhs_snoc_cfg,
&qhs_emac_cfg,
&qhs_usb3,
&qhs_tlmm,
&qhs_spmi_fetcher,
&qhs_qdss_cfg,
&qhs_pdm,
&qns_snoc_memnoc,
&qhs_tcsr,
&qhs_ddrss_cfg,
&qhs_spmi_vgi_coex,
&qhs_qpic,
&qxs_imem,
&qhs_ipa,
&qhs_usb3_phy,
&qhs_aop,
&qhs_blsp1,
&qhs_sdc1,
&qhs_mss_cfg,
&qhs_pcie_parf,
&qhs_ecc_cfg,
&qhs_audio,
&qhs_aoss,
&qhs_prng,
&qhs_crypto0_cfg,
&xs_sys_tcu_cfg,
&qhs_clk_ctl,
&qhs_imem_cfg },
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
.id = SDX55_MASTER_QPIC,
.channels = 1,
.buswidth = 4,
.num_links = 5,
.links = { SDX55_SLAVE_AOSS,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_ANOC_SNOC,
SDX55_SLAVE_AOP,
SDX55_SLAVE_AUDIO
},
.link_nodes = { &qhs_aoss,
&qhs_ipa,
&qns_aggre_noc,
&qhs_aop,
&qhs_audio },
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
.id = SDX55_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX55_SLAVE_SERVICE_SNOC },
.link_nodes = { &srvc_snoc },
};
static struct qcom_icc_node qhm_spmi_fetcher1 = {
.name = "qhm_spmi_fetcher1",
.id = SDX55_MASTER_SPMI_FETCHER,
.channels = 1,
.buswidth = 4,
.num_links = 3,
.links = { SDX55_SLAVE_AOSS,
SDX55_SLAVE_ANOC_SNOC,
SDX55_SLAVE_AOP
},
.link_nodes = { &qhs_aoss,
&qns_aggre_noc,
&qhs_aop },
};
static struct qcom_icc_node qnm_aggre_noc = {
.name = "qnm_aggre_noc",
.id = SDX55_MASTER_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 30,
.links = { SDX55_SLAVE_PCIE_0,
SDX55_SLAVE_SNOC_CFG,
SDX55_SLAVE_SDCC_1,
SDX55_SLAVE_TLMM,
SDX55_SLAVE_SPMI_FETCHER,
SDX55_SLAVE_QDSS_CFG,
SDX55_SLAVE_PDM,
SDX55_SLAVE_SNOC_MEM_NOC_GC,
SDX55_SLAVE_TCSR,
SDX55_SLAVE_CNOC_DDRSS,
SDX55_SLAVE_SPMI_VGI_COEX,
SDX55_SLAVE_QDSS_STM,
SDX55_SLAVE_QPIC,
SDX55_SLAVE_OCIMEM,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_USB3_PHY_CFG,
SDX55_SLAVE_AOP,
SDX55_SLAVE_BLSP_1,
SDX55_SLAVE_USB3,
SDX55_SLAVE_CNOC_MSS,
SDX55_SLAVE_PCIE_PARF,
SDX55_SLAVE_ECC_CFG,
SDX55_SLAVE_APPSS,
SDX55_SLAVE_AUDIO,
SDX55_SLAVE_AOSS,
SDX55_SLAVE_PRNG,
SDX55_SLAVE_CRYPTO_0_CFG,
SDX55_SLAVE_TCU,
SDX55_SLAVE_CLK_CTL,
SDX55_SLAVE_IMEM_CFG
},
.link_nodes = { &xs_pcie,
&qhs_snoc_cfg,
&qhs_sdc1,
&qhs_tlmm,
&qhs_spmi_fetcher,
&qhs_qdss_cfg,
&qhs_pdm,
&qns_snoc_memnoc,
&qhs_tcsr,
&qhs_ddrss_cfg,
&qhs_spmi_vgi_coex,
&xs_qdss_stm,
&qhs_qpic,
&qxs_imem,
&qhs_ipa,
&qhs_usb3_phy,
&qhs_aop,
&qhs_blsp1,
&qhs_usb3,
&qhs_mss_cfg,
&qhs_pcie_parf,
&qhs_ecc_cfg,
&qhs_apss,
&qhs_audio,
&qhs_aoss,
&qhs_prng,
&qhs_crypto0_cfg,
&xs_sys_tcu_cfg,
&qhs_clk_ctl,
&qhs_imem_cfg },
};
static struct qcom_icc_node qnm_ipa = {
.name = "qnm_ipa",
.id = SDX55_MASTER_IPA,
.channels = 1,
.buswidth = 8,
.num_links = 27,
.links = { SDX55_SLAVE_SNOC_CFG,
SDX55_SLAVE_EMAC_CFG,
SDX55_SLAVE_USB3,
SDX55_SLAVE_AOSS,
SDX55_SLAVE_SPMI_FETCHER,
SDX55_SLAVE_QDSS_CFG,
SDX55_SLAVE_PDM,
SDX55_SLAVE_SNOC_MEM_NOC_GC,
SDX55_SLAVE_TCSR,
SDX55_SLAVE_CNOC_DDRSS,
SDX55_SLAVE_QDSS_STM,
SDX55_SLAVE_QPIC,
SDX55_SLAVE_OCIMEM,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_USB3_PHY_CFG,
SDX55_SLAVE_AOP,
SDX55_SLAVE_BLSP_1,
SDX55_SLAVE_SDCC_1,
SDX55_SLAVE_CNOC_MSS,
SDX55_SLAVE_PCIE_PARF,
SDX55_SLAVE_ECC_CFG,
SDX55_SLAVE_AUDIO,
SDX55_SLAVE_TLMM,
SDX55_SLAVE_PRNG,
SDX55_SLAVE_CRYPTO_0_CFG,
SDX55_SLAVE_CLK_CTL,
SDX55_SLAVE_IMEM_CFG
},
.link_nodes = { &qhs_snoc_cfg,
&qhs_emac_cfg,
&qhs_usb3,
&qhs_aoss,
&qhs_spmi_fetcher,
&qhs_qdss_cfg,
&qhs_pdm,
&qns_snoc_memnoc,
&qhs_tcsr,
&qhs_ddrss_cfg,
&xs_qdss_stm,
&qhs_qpic,
&qxs_imem,
&qhs_ipa,
&qhs_usb3_phy,
&qhs_aop,
&qhs_blsp1,
&qhs_sdc1,
&qhs_mss_cfg,
&qhs_pcie_parf,
&qhs_ecc_cfg,
&qhs_audio,
&qhs_tlmm,
&qhs_prng,
&qhs_crypto0_cfg,
&qhs_clk_ctl,
&qhs_imem_cfg },
};
static struct qcom_icc_node qnm_memnoc = {
.name = "qnm_memnoc",
.id = SDX55_MASTER_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 29,
.links = { SDX55_SLAVE_SNOC_CFG,
SDX55_SLAVE_EMAC_CFG,
SDX55_SLAVE_USB3,
SDX55_SLAVE_TLMM,
SDX55_SLAVE_SPMI_FETCHER,
SDX55_SLAVE_QDSS_CFG,
SDX55_SLAVE_PDM,
SDX55_SLAVE_TCSR,
SDX55_SLAVE_CNOC_DDRSS,
SDX55_SLAVE_SPMI_VGI_COEX,
SDX55_SLAVE_QDSS_STM,
SDX55_SLAVE_QPIC,
SDX55_SLAVE_OCIMEM,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_USB3_PHY_CFG,
SDX55_SLAVE_AOP,
SDX55_SLAVE_BLSP_1,
SDX55_SLAVE_SDCC_1,
SDX55_SLAVE_CNOC_MSS,
SDX55_SLAVE_PCIE_PARF,
SDX55_SLAVE_ECC_CFG,
SDX55_SLAVE_APPSS,
SDX55_SLAVE_AUDIO,
SDX55_SLAVE_AOSS,
SDX55_SLAVE_PRNG,
SDX55_SLAVE_CRYPTO_0_CFG,
SDX55_SLAVE_TCU,
SDX55_SLAVE_CLK_CTL,
SDX55_SLAVE_IMEM_CFG
},
.link_nodes = { &qhs_snoc_cfg,
&qhs_emac_cfg,
&qhs_usb3,
&qhs_tlmm,
&qhs_spmi_fetcher,
&qhs_qdss_cfg,
&qhs_pdm,
&qhs_tcsr,
&qhs_ddrss_cfg,
&qhs_spmi_vgi_coex,
&xs_qdss_stm,
&qhs_qpic,
&qxs_imem,
&qhs_ipa,
&qhs_usb3_phy,
&qhs_aop,
&qhs_blsp1,
&qhs_sdc1,
&qhs_mss_cfg,
&qhs_pcie_parf,
&qhs_ecc_cfg,
&qhs_apss,
&qhs_audio,
&qhs_aoss,
&qhs_prng,
&qhs_crypto0_cfg,
&xs_sys_tcu_cfg,
&qhs_clk_ctl,
&qhs_imem_cfg },
};
static struct qcom_icc_node qnm_memnoc_pcie = {
.name = "qnm_memnoc_pcie",
.id = SDX55_MASTER_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_SLAVE_PCIE_0 },
.link_nodes = { &xs_pcie },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
.id = SDX55_MASTER_CRYPTO_CORE_0,
.channels = 1,
.buswidth = 8,
.num_links = 3,
.links = { SDX55_SLAVE_AOSS,
SDX55_SLAVE_ANOC_SNOC,
SDX55_SLAVE_AOP
},
.link_nodes = { &qhs_aoss,
&qns_aggre_noc,
&qhs_aop },
};
static struct qcom_icc_node xm_emac = {
.name = "xm_emac",
.id = SDX55_MASTER_EMAC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_SLAVE_ANOC_SNOC },
.link_nodes = { &qns_aggre_noc },
};
static struct qcom_icc_node xm_ipa2pcie_slv = {
.name = "xm_ipa2pcie_slv",
.id = SDX55_MASTER_IPA_PCIE,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_SLAVE_PCIE_0 },
.link_nodes = { &xs_pcie },
};
static struct qcom_icc_node xm_pcie = {
.name = "xm_pcie",
.id = SDX55_MASTER_PCIE,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_SLAVE_ANOC_SNOC },
.link_nodes = { &qns_aggre_noc },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
.id = SDX55_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
.num_links = 28,
.links = { SDX55_SLAVE_SNOC_CFG,
SDX55_SLAVE_EMAC_CFG,
SDX55_SLAVE_USB3,
SDX55_SLAVE_AOSS,
SDX55_SLAVE_SPMI_FETCHER,
SDX55_SLAVE_QDSS_CFG,
SDX55_SLAVE_PDM,
SDX55_SLAVE_SNOC_MEM_NOC_GC,
SDX55_SLAVE_TCSR,
SDX55_SLAVE_CNOC_DDRSS,
SDX55_SLAVE_SPMI_VGI_COEX,
SDX55_SLAVE_QPIC,
SDX55_SLAVE_OCIMEM,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_USB3_PHY_CFG,
SDX55_SLAVE_AOP,
SDX55_SLAVE_BLSP_1,
SDX55_SLAVE_SDCC_1,
SDX55_SLAVE_CNOC_MSS,
SDX55_SLAVE_PCIE_PARF,
SDX55_SLAVE_ECC_CFG,
SDX55_SLAVE_AUDIO,
SDX55_SLAVE_AOSS,
SDX55_SLAVE_PRNG,
SDX55_SLAVE_CRYPTO_0_CFG,
SDX55_SLAVE_TCU,
SDX55_SLAVE_CLK_CTL,
SDX55_SLAVE_IMEM_CFG
},
.link_nodes = { &qhs_snoc_cfg,
&qhs_emac_cfg,
&qhs_usb3,
&qhs_aoss,
&qhs_spmi_fetcher,
&qhs_qdss_cfg,
&qhs_pdm,
&qns_snoc_memnoc,
&qhs_tcsr,
&qhs_ddrss_cfg,
&qhs_spmi_vgi_coex,
&qhs_qpic,
&qxs_imem,
&qhs_ipa,
&qhs_usb3_phy,
&qhs_aop,
&qhs_blsp1,
&qhs_sdc1,
&qhs_mss_cfg,
&qhs_pcie_parf,
&qhs_ecc_cfg,
&qhs_audio,
&qhs_aoss,
&qhs_prng,
&qhs_crypto0_cfg,
&xs_sys_tcu_cfg,
&qhs_clk_ctl,
&qhs_imem_cfg },
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
.id = SDX55_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
.num_links = 5,
.links = { SDX55_SLAVE_AOSS,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_ANOC_SNOC,
SDX55_SLAVE_AOP,
SDX55_SLAVE_AUDIO
},
.link_nodes = { &qhs_aoss,
&qhs_ipa,
&qns_aggre_noc,
&qhs_aop,
&qhs_audio },
};
static struct qcom_icc_node xm_usb3 = {
.name = "xm_usb3",
.id = SDX55_MASTER_USB3,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_SLAVE_ANOC_SNOC },
.link_nodes = { &qns_aggre_noc },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
.id = SDX55_SLAVE_EBI_CH0,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
.id = SDX55_SLAVE_LLCC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SDX55_SLAVE_EBI_CH0 },
.link_nodes = { &ebi },
};
static struct qcom_icc_node qns_memnoc_snoc = {
.name = "qns_memnoc_snoc",
.id = SDX55_SLAVE_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_MASTER_MEM_NOC_SNOC },
.link_nodes = { &qnm_memnoc },
};
static struct qcom_icc_node qns_sys_pcie = {
.name = "qns_sys_pcie",
.id = SDX55_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_MASTER_MEM_NOC_PCIE_SNOC },
.link_nodes = { &qnm_memnoc_pcie },
};
static struct qcom_icc_node qhs_aop = {
.name = "qhs_aop",
.id = SDX55_SLAVE_AOP,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
.id = SDX55_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
.id = SDX55_SLAVE_APPSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_audio = {
.name = "qhs_audio",
.id = SDX55_SLAVE_AUDIO,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_blsp1 = {
.name = "qhs_blsp1",
.id = SDX55_SLAVE_BLSP_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
.id = SDX55_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
.id = SDX55_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
.id = SDX55_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ecc_cfg = {
.name = "qhs_ecc_cfg",
.id = SDX55_SLAVE_ECC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_emac_cfg = {
.name = "qhs_emac_cfg",
.id = SDX55_SLAVE_EMAC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
.id = SDX55_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
.id = SDX55_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
.id = SDX55_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pcie_parf = {
.name = "qhs_pcie_parf",
.id = SDX55_SLAVE_PCIE_PARF,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
.id = SDX55_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
.id = SDX55_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
.id = SDX55_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qpic = {
.name = "qhs_qpic",
.id = SDX55_SLAVE_QPIC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
.id = SDX55_SLAVE_SDCC_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
.id = SDX55_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX55_MASTER_SNOC_CFG },
.link_nodes = { &qhm_snoc_cfg },
};
static struct qcom_icc_node qhs_spmi_fetcher = {
.name = "qhs_spmi_fetcher",
.id = SDX55_SLAVE_SPMI_FETCHER,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_spmi_vgi_coex = {
.name = "qhs_spmi_vgi_coex",
.id = SDX55_SLAVE_SPMI_VGI_COEX,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
.id = SDX55_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
.id = SDX55_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
.id = SDX55_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_usb3_phy = {
.name = "qhs_usb3_phy",
.id = SDX55_SLAVE_USB3_PHY_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_aggre_noc = {
.name = "qns_aggre_noc",
.id = SDX55_SLAVE_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_MASTER_ANOC_SNOC },
.link_nodes = { &qnm_aggre_noc },
};
static struct qcom_icc_node qns_snoc_memnoc = {
.name = "qns_snoc_memnoc",
.id = SDX55_SLAVE_SNOC_MEM_NOC_GC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_MASTER_SNOC_GC_MEM_NOC },
.link_nodes = { &qnm_snoc_gc },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
.id = SDX55_SLAVE_OCIMEM,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
.id = SDX55_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node xs_pcie = {
.name = "xs_pcie",
.id = SDX55_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
.id = SDX55_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
.id = SDX55_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
};

70
drivers/interconnect/qcom/sdx55.h
View File

@@ -1,70 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021, Linaro Ltd.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H
#define __DRIVERS_INTERCONNECT_QCOM_SDX55_H
/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */
#define SDX55_MASTER_LLCC 1
#define SDX55_MASTER_TCU_0 2
#define SDX55_MASTER_SNOC_GC_MEM_NOC 3
#define SDX55_MASTER_AMPSS_M0 4
#define SDX55_MASTER_AUDIO 5
#define SDX55_MASTER_BLSP_1 6
#define SDX55_MASTER_QDSS_BAM 7
#define SDX55_MASTER_QPIC 8
#define SDX55_MASTER_SNOC_CFG 9
#define SDX55_MASTER_SPMI_FETCHER 10
#define SDX55_MASTER_ANOC_SNOC 11
#define SDX55_MASTER_IPA 12
#define SDX55_MASTER_MEM_NOC_SNOC 13
#define SDX55_MASTER_MEM_NOC_PCIE_SNOC 14
#define SDX55_MASTER_CRYPTO_CORE_0 15
#define SDX55_MASTER_EMAC 16
#define SDX55_MASTER_IPA_PCIE 17
#define SDX55_MASTER_PCIE 18
#define SDX55_MASTER_QDSS_ETR 19
#define SDX55_MASTER_SDCC_1 20
#define SDX55_MASTER_USB3 21
/* 22 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SDX55_SLAVE_EBI_CH0 23
#define SDX55_SLAVE_LLCC 24
#define SDX55_SLAVE_MEM_NOC_SNOC 25
#define SDX55_SLAVE_MEM_NOC_PCIE_SNOC 26
#define SDX55_SLAVE_ANOC_SNOC 27
#define SDX55_SLAVE_SNOC_CFG 28
#define SDX55_SLAVE_EMAC_CFG 29
#define SDX55_SLAVE_USB3 30
#define SDX55_SLAVE_TLMM 31
#define SDX55_SLAVE_SPMI_FETCHER 32
#define SDX55_SLAVE_QDSS_CFG 33
#define SDX55_SLAVE_PDM 34
#define SDX55_SLAVE_SNOC_MEM_NOC_GC 35
#define SDX55_SLAVE_TCSR 36
#define SDX55_SLAVE_CNOC_DDRSS 37
#define SDX55_SLAVE_SPMI_VGI_COEX 38
#define SDX55_SLAVE_QPIC 39
#define SDX55_SLAVE_OCIMEM 40
#define SDX55_SLAVE_IPA_CFG 41
#define SDX55_SLAVE_USB3_PHY_CFG 42
#define SDX55_SLAVE_AOP 43
#define SDX55_SLAVE_BLSP_1 44
#define SDX55_SLAVE_SDCC_1 45
#define SDX55_SLAVE_CNOC_MSS 46
#define SDX55_SLAVE_PCIE_PARF 47
#define SDX55_SLAVE_ECC_CFG 48
#define SDX55_SLAVE_AUDIO 49
#define SDX55_SLAVE_AOSS 51
#define SDX55_SLAVE_PRNG 52
#define SDX55_SLAVE_CRYPTO_0_CFG 53
#define SDX55_SLAVE_TCU 54
#define SDX55_SLAVE_CLK_CTL 55
#define SDX55_SLAVE_IMEM_CFG 56
#define SDX55_SLAVE_SERVICE_SNOC 57
#define SDX55_SLAVE_PCIE_0 58
#define SDX55_SLAVE_QDSS_STM 59
#define SDX55_SLAVE_APPSS 60
#endif

457
drivers/interconnect/qcom/sdx65.c
View File

@@ -13,593 +13,582 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
#include "sdx65.h"
static struct qcom_icc_node llcc_mc;
static struct qcom_icc_node acm_tcu;
static struct qcom_icc_node qnm_snoc_gc;
static struct qcom_icc_node xm_apps_rdwr;
static struct qcom_icc_node qhm_audio;
static struct qcom_icc_node qhm_blsp1;
static struct qcom_icc_node qhm_qdss_bam;
static struct qcom_icc_node qhm_qpic;
static struct qcom_icc_node qhm_snoc_cfg;
static struct qcom_icc_node qhm_spmi_fetcher1;
static struct qcom_icc_node qnm_aggre_noc;
static struct qcom_icc_node qnm_ipa;
static struct qcom_icc_node qnm_memnoc;
static struct qcom_icc_node qnm_memnoc_pcie;
static struct qcom_icc_node qxm_crypto;
static struct qcom_icc_node xm_ipa2pcie_slv;
static struct qcom_icc_node xm_pcie;
static struct qcom_icc_node xm_qdss_etr;
static struct qcom_icc_node xm_sdc1;
static struct qcom_icc_node xm_usb3;
static struct qcom_icc_node ebi;
static struct qcom_icc_node qns_llcc;
static struct qcom_icc_node qns_memnoc_snoc;
static struct qcom_icc_node qns_sys_pcie;
static struct qcom_icc_node qhs_aoss;
static struct qcom_icc_node qhs_apss;
static struct qcom_icc_node qhs_audio;
static struct qcom_icc_node qhs_blsp1;
static struct qcom_icc_node qhs_clk_ctl;
static struct qcom_icc_node qhs_crypto0_cfg;
static struct qcom_icc_node qhs_ddrss_cfg;
static struct qcom_icc_node qhs_ecc_cfg;
static struct qcom_icc_node qhs_imem_cfg;
static struct qcom_icc_node qhs_ipa;
static struct qcom_icc_node qhs_mss_cfg;
static struct qcom_icc_node qhs_pcie_parf;
static struct qcom_icc_node qhs_pdm;
static struct qcom_icc_node qhs_prng;
static struct qcom_icc_node qhs_qdss_cfg;
static struct qcom_icc_node qhs_qpic;
static struct qcom_icc_node qhs_sdc1;
static struct qcom_icc_node qhs_snoc_cfg;
static struct qcom_icc_node qhs_spmi_fetcher;
static struct qcom_icc_node qhs_spmi_vgi_coex;
static struct qcom_icc_node qhs_tcsr;
static struct qcom_icc_node qhs_tlmm;
static struct qcom_icc_node qhs_usb3;
static struct qcom_icc_node qhs_usb3_phy;
static struct qcom_icc_node qns_aggre_noc;
static struct qcom_icc_node qns_snoc_memnoc;
static struct qcom_icc_node qxs_imem;
static struct qcom_icc_node srvc_snoc;
static struct qcom_icc_node xs_pcie;
static struct qcom_icc_node xs_qdss_stm;
static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
.id = SDX65_MASTER_LLCC,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_SLAVE_EBI1 },
.link_nodes = { &ebi },
};
static struct qcom_icc_node acm_tcu = {
.name = "acm_tcu",
.id = SDX65_MASTER_TCU_0,
.channels = 1,
.buswidth = 8,
.num_links = 3,
.links = { SDX65_SLAVE_LLCC,
SDX65_SLAVE_MEM_NOC_SNOC,
SDX65_SLAVE_MEM_NOC_PCIE_SNOC
},
.link_nodes = { &qns_llcc,
&qns_memnoc_snoc,
&qns_sys_pcie },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
.id = SDX65_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SDX65_SLAVE_LLCC },
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_node xm_apps_rdwr = {
.name = "xm_apps_rdwr",
.id = SDX65_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 16,
.num_links = 3,
.links = { SDX65_SLAVE_LLCC,
SDX65_SLAVE_MEM_NOC_SNOC,
SDX65_SLAVE_MEM_NOC_PCIE_SNOC
},
.link_nodes = { &qns_llcc,
&qns_memnoc_snoc,
&qns_sys_pcie },
};
static struct qcom_icc_node qhm_audio = {
.name = "qhm_audio",
.id = SDX65_MASTER_AUDIO,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_SLAVE_ANOC_SNOC },
.link_nodes = { &qns_aggre_noc },
};
static struct qcom_icc_node qhm_blsp1 = {
.name = "qhm_blsp1",
.id = SDX65_MASTER_BLSP_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_SLAVE_ANOC_SNOC },
.link_nodes = { &qns_aggre_noc },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.id = SDX65_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.num_links = 26,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_BLSP_1,
SDX65_SLAVE_CLK_CTL,
SDX65_SLAVE_CRYPTO_0_CFG,
SDX65_SLAVE_CNOC_DDRSS,
SDX65_SLAVE_ECC_CFG,
SDX65_SLAVE_IMEM_CFG,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_CNOC_MSS,
SDX65_SLAVE_PCIE_PARF,
SDX65_SLAVE_PDM,
SDX65_SLAVE_PRNG,
SDX65_SLAVE_QDSS_CFG,
SDX65_SLAVE_QPIC,
SDX65_SLAVE_SDCC_1,
SDX65_SLAVE_SNOC_CFG,
SDX65_SLAVE_SPMI_FETCHER,
SDX65_SLAVE_SPMI_VGI_COEX,
SDX65_SLAVE_TCSR,
SDX65_SLAVE_TLMM,
SDX65_SLAVE_USB3,
SDX65_SLAVE_USB3_PHY_CFG,
SDX65_SLAVE_SNOC_MEM_NOC_GC,
SDX65_SLAVE_IMEM,
SDX65_SLAVE_TCU
},
.link_nodes = { &qhs_aoss,
&qhs_audio,
&qhs_blsp1,
&qhs_clk_ctl,
&qhs_crypto0_cfg,
&qhs_ddrss_cfg,
&qhs_ecc_cfg,
&qhs_imem_cfg,
&qhs_ipa,
&qhs_mss_cfg,
&qhs_pcie_parf,
&qhs_pdm,
&qhs_prng,
&qhs_qdss_cfg,
&qhs_qpic,
&qhs_sdc1,
&qhs_snoc_cfg,
&qhs_spmi_fetcher,
&qhs_spmi_vgi_coex,
&qhs_tcsr,
&qhs_tlmm,
&qhs_usb3,
&qhs_usb3_phy,
&qns_snoc_memnoc,
&qxs_imem,
&xs_sys_tcu_cfg },
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
.id = SDX65_MASTER_QPIC,
.channels = 1,
.buswidth = 4,
.num_links = 4,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_ANOC_SNOC
},
.link_nodes = { &qhs_aoss,
&qhs_audio,
&qhs_ipa,
&qns_aggre_noc },
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
.id = SDX65_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_SLAVE_SERVICE_SNOC },
.link_nodes = { &srvc_snoc },
};
static struct qcom_icc_node qhm_spmi_fetcher1 = {
.name = "qhm_spmi_fetcher1",
.id = SDX65_MASTER_SPMI_FETCHER,
.channels = 1,
.buswidth = 4,
.num_links = 2,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_ANOC_SNOC
},
.link_nodes = { &qhs_aoss,
&qns_aggre_noc },
};
static struct qcom_icc_node qnm_aggre_noc = {
.name = "qnm_aggre_noc",
.id = SDX65_MASTER_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 29,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_APPSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_BLSP_1,
SDX65_SLAVE_CLK_CTL,
SDX65_SLAVE_CRYPTO_0_CFG,
SDX65_SLAVE_CNOC_DDRSS,
SDX65_SLAVE_ECC_CFG,
SDX65_SLAVE_IMEM_CFG,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_CNOC_MSS,
SDX65_SLAVE_PCIE_PARF,
SDX65_SLAVE_PDM,
SDX65_SLAVE_PRNG,
SDX65_SLAVE_QDSS_CFG,
SDX65_SLAVE_QPIC,
SDX65_SLAVE_SDCC_1,
SDX65_SLAVE_SNOC_CFG,
SDX65_SLAVE_SPMI_FETCHER,
SDX65_SLAVE_SPMI_VGI_COEX,
SDX65_SLAVE_TCSR,
SDX65_SLAVE_TLMM,
SDX65_SLAVE_USB3,
SDX65_SLAVE_USB3_PHY_CFG,
SDX65_SLAVE_SNOC_MEM_NOC_GC,
SDX65_SLAVE_IMEM,
SDX65_SLAVE_PCIE_0,
SDX65_SLAVE_QDSS_STM,
SDX65_SLAVE_TCU
},
.link_nodes = { &qhs_aoss,
&qhs_apss,
&qhs_audio,
&qhs_blsp1,
&qhs_clk_ctl,
&qhs_crypto0_cfg,
&qhs_ddrss_cfg,
&qhs_ecc_cfg,
&qhs_imem_cfg,
&qhs_ipa,
&qhs_mss_cfg,
&qhs_pcie_parf,
&qhs_pdm,
&qhs_prng,
&qhs_qdss_cfg,
&qhs_qpic,
&qhs_sdc1,
&qhs_snoc_cfg,
&qhs_spmi_fetcher,
&qhs_spmi_vgi_coex,
&qhs_tcsr,
&qhs_tlmm,
&qhs_usb3,
&qhs_usb3_phy,
&qns_snoc_memnoc,
&qxs_imem,
&xs_pcie,
&xs_qdss_stm,
&xs_sys_tcu_cfg },
};
static struct qcom_icc_node qnm_ipa = {
.name = "qnm_ipa",
.id = SDX65_MASTER_IPA,
.channels = 1,
.buswidth = 8,
.num_links = 26,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_BLSP_1,
SDX65_SLAVE_CLK_CTL,
SDX65_SLAVE_CRYPTO_0_CFG,
SDX65_SLAVE_CNOC_DDRSS,
SDX65_SLAVE_ECC_CFG,
SDX65_SLAVE_IMEM_CFG,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_CNOC_MSS,
SDX65_SLAVE_PCIE_PARF,
SDX65_SLAVE_PDM,
SDX65_SLAVE_PRNG,
SDX65_SLAVE_QDSS_CFG,
SDX65_SLAVE_QPIC,
SDX65_SLAVE_SDCC_1,
SDX65_SLAVE_SNOC_CFG,
SDX65_SLAVE_SPMI_FETCHER,
SDX65_SLAVE_TCSR,
SDX65_SLAVE_TLMM,
SDX65_SLAVE_USB3,
SDX65_SLAVE_USB3_PHY_CFG,
SDX65_SLAVE_SNOC_MEM_NOC_GC,
SDX65_SLAVE_IMEM,
SDX65_SLAVE_PCIE_0,
SDX65_SLAVE_QDSS_STM
},
.link_nodes = { &qhs_aoss,
&qhs_audio,
&qhs_blsp1,
&qhs_clk_ctl,
&qhs_crypto0_cfg,
&qhs_ddrss_cfg,
&qhs_ecc_cfg,
&qhs_imem_cfg,
&qhs_ipa,
&qhs_mss_cfg,
&qhs_pcie_parf,
&qhs_pdm,
&qhs_prng,
&qhs_qdss_cfg,
&qhs_qpic,
&qhs_sdc1,
&qhs_snoc_cfg,
&qhs_spmi_fetcher,
&qhs_tcsr,
&qhs_tlmm,
&qhs_usb3,
&qhs_usb3_phy,
&qns_snoc_memnoc,
&qxs_imem,
&xs_pcie,
&xs_qdss_stm },
};
static struct qcom_icc_node qnm_memnoc = {
.name = "qnm_memnoc",
.id = SDX65_MASTER_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 27,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_APPSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_BLSP_1,
SDX65_SLAVE_CLK_CTL,
SDX65_SLAVE_CRYPTO_0_CFG,
SDX65_SLAVE_CNOC_DDRSS,
SDX65_SLAVE_ECC_CFG,
SDX65_SLAVE_IMEM_CFG,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_CNOC_MSS,
SDX65_SLAVE_PCIE_PARF,
SDX65_SLAVE_PDM,
SDX65_SLAVE_PRNG,
SDX65_SLAVE_QDSS_CFG,
SDX65_SLAVE_QPIC,
SDX65_SLAVE_SDCC_1,
SDX65_SLAVE_SNOC_CFG,
SDX65_SLAVE_SPMI_FETCHER,
SDX65_SLAVE_SPMI_VGI_COEX,
SDX65_SLAVE_TCSR,
SDX65_SLAVE_TLMM,
SDX65_SLAVE_USB3,
SDX65_SLAVE_USB3_PHY_CFG,
SDX65_SLAVE_IMEM,
SDX65_SLAVE_QDSS_STM,
SDX65_SLAVE_TCU
},
.link_nodes = { &qhs_aoss,
&qhs_apss,
&qhs_audio,
&qhs_blsp1,
&qhs_clk_ctl,
&qhs_crypto0_cfg,
&qhs_ddrss_cfg,
&qhs_ecc_cfg,
&qhs_imem_cfg,
&qhs_ipa,
&qhs_mss_cfg,
&qhs_pcie_parf,
&qhs_pdm,
&qhs_prng,
&qhs_qdss_cfg,
&qhs_qpic,
&qhs_sdc1,
&qhs_snoc_cfg,
&qhs_spmi_fetcher,
&qhs_spmi_vgi_coex,
&qhs_tcsr,
&qhs_tlmm,
&qhs_usb3,
&qhs_usb3_phy,
&qxs_imem,
&xs_qdss_stm,
&xs_sys_tcu_cfg },
};
static struct qcom_icc_node qnm_memnoc_pcie = {
.name = "qnm_memnoc_pcie",
.id = SDX65_MASTER_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_SLAVE_PCIE_0 },
.link_nodes = { &xs_pcie },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
.id = SDX65_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
.num_links = 2,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_ANOC_SNOC
},
.link_nodes = { &qhs_aoss,
&qns_aggre_noc },
};
static struct qcom_icc_node xm_ipa2pcie_slv = {
.name = "xm_ipa2pcie_slv",
.id = SDX65_MASTER_IPA_PCIE,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_SLAVE_PCIE_0 },
.link_nodes = { &xs_pcie },
};
static struct qcom_icc_node xm_pcie = {
.name = "xm_pcie",
.id = SDX65_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_SLAVE_ANOC_SNOC },
.link_nodes = { &qns_aggre_noc },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
.id = SDX65_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
.num_links = 26,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_BLSP_1,
SDX65_SLAVE_CLK_CTL,
SDX65_SLAVE_CRYPTO_0_CFG,
SDX65_SLAVE_CNOC_DDRSS,
SDX65_SLAVE_ECC_CFG,
SDX65_SLAVE_IMEM_CFG,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_CNOC_MSS,
SDX65_SLAVE_PCIE_PARF,
SDX65_SLAVE_PDM,
SDX65_SLAVE_PRNG,
SDX65_SLAVE_QDSS_CFG,
SDX65_SLAVE_QPIC,
SDX65_SLAVE_SDCC_1,
SDX65_SLAVE_SNOC_CFG,
SDX65_SLAVE_SPMI_FETCHER,
SDX65_SLAVE_SPMI_VGI_COEX,
SDX65_SLAVE_TCSR,
SDX65_SLAVE_TLMM,
SDX65_SLAVE_USB3,
SDX65_SLAVE_USB3_PHY_CFG,
SDX65_SLAVE_SNOC_MEM_NOC_GC,
SDX65_SLAVE_IMEM,
SDX65_SLAVE_TCU
},
.link_nodes = { &qhs_aoss,
&qhs_audio,
&qhs_blsp1,
&qhs_clk_ctl,
&qhs_crypto0_cfg,
&qhs_ddrss_cfg,
&qhs_ecc_cfg,
&qhs_imem_cfg,
&qhs_ipa,
&qhs_mss_cfg,
&qhs_pcie_parf,
&qhs_pdm,
&qhs_prng,
&qhs_qdss_cfg,
&qhs_qpic,
&qhs_sdc1,
&qhs_snoc_cfg,
&qhs_spmi_fetcher,
&qhs_spmi_vgi_coex,
&qhs_tcsr,
&qhs_tlmm,
&qhs_usb3,
&qhs_usb3_phy,
&qns_snoc_memnoc,
&qxs_imem,
&xs_sys_tcu_cfg },
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
.id = SDX65_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
.num_links = 4,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_ANOC_SNOC
},
.link_nodes = { &qhs_aoss,
&qhs_audio,
&qhs_ipa,
&qns_aggre_noc },
};
static struct qcom_icc_node xm_usb3 = {
.name = "xm_usb3",
.id = SDX65_MASTER_USB3,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_SLAVE_ANOC_SNOC },
.link_nodes = { &qns_aggre_noc },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
.id = SDX65_SLAVE_EBI1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
.id = SDX65_SLAVE_LLCC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SDX65_MASTER_LLCC },
.link_nodes = { &llcc_mc },
};
static struct qcom_icc_node qns_memnoc_snoc = {
.name = "qns_memnoc_snoc",
.id = SDX65_SLAVE_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_MASTER_MEM_NOC_SNOC },
.link_nodes = { &qnm_memnoc },
};
static struct qcom_icc_node qns_sys_pcie = {
.name = "qns_sys_pcie",
.id = SDX65_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_MASTER_MEM_NOC_PCIE_SNOC },
.link_nodes = { &qnm_memnoc_pcie },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
.id = SDX65_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
.id = SDX65_SLAVE_APPSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_audio = {
.name = "qhs_audio",
.id = SDX65_SLAVE_AUDIO,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_blsp1 = {
.name = "qhs_blsp1",
.id = SDX65_SLAVE_BLSP_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
.id = SDX65_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
.id = SDX65_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
.id = SDX65_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ecc_cfg = {
.name = "qhs_ecc_cfg",
.id = SDX65_SLAVE_ECC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
.id = SDX65_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
.id = SDX65_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
.id = SDX65_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pcie_parf = {
.name = "qhs_pcie_parf",
.id = SDX65_SLAVE_PCIE_PARF,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
.id = SDX65_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
.id = SDX65_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
.id = SDX65_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qpic = {
.name = "qhs_qpic",
.id = SDX65_SLAVE_QPIC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
.id = SDX65_SLAVE_SDCC_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
.id = SDX65_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_MASTER_SNOC_CFG },
.link_nodes = { &qhm_snoc_cfg },
};
static struct qcom_icc_node qhs_spmi_fetcher = {
.name = "qhs_spmi_fetcher",
.id = SDX65_SLAVE_SPMI_FETCHER,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_spmi_vgi_coex = {
.name = "qhs_spmi_vgi_coex",
.id = SDX65_SLAVE_SPMI_VGI_COEX,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
.id = SDX65_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
.id = SDX65_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
.id = SDX65_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_usb3_phy = {
.name = "qhs_usb3_phy",
.id = SDX65_SLAVE_USB3_PHY_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_aggre_noc = {
.name = "qns_aggre_noc",
.id = SDX65_SLAVE_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_MASTER_ANOC_SNOC },
.link_nodes = { &qnm_aggre_noc },
};
static struct qcom_icc_node qns_snoc_memnoc = {
.name = "qns_snoc_memnoc",
.id = SDX65_SLAVE_SNOC_MEM_NOC_GC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SDX65_MASTER_SNOC_GC_MEM_NOC },
.link_nodes = { &qnm_snoc_gc },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
.id = SDX65_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
.id = SDX65_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node xs_pcie = {
.name = "xs_pcie",
.id = SDX65_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
.id = SDX65_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
.id = SDX65_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
};

65
drivers/interconnect/qcom/sdx65.h
View File

@@ -1,65 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX65_H
#define __DRIVERS_INTERCONNECT_QCOM_SDX65_H
#define SDX65_MASTER_TCU_0 0
#define SDX65_MASTER_LLCC 1
#define SDX65_MASTER_AUDIO 2
#define SDX65_MASTER_BLSP_1 3
#define SDX65_MASTER_QDSS_BAM 4
#define SDX65_MASTER_QPIC 5
#define SDX65_MASTER_SNOC_CFG 6
#define SDX65_MASTER_SPMI_FETCHER 7
#define SDX65_MASTER_ANOC_SNOC 8
#define SDX65_MASTER_IPA 9
#define SDX65_MASTER_MEM_NOC_SNOC 10
#define SDX65_MASTER_MEM_NOC_PCIE_SNOC 11
#define SDX65_MASTER_SNOC_GC_MEM_NOC 12
#define SDX65_MASTER_CRYPTO 13
#define SDX65_MASTER_APPSS_PROC 14
#define SDX65_MASTER_IPA_PCIE 15
#define SDX65_MASTER_PCIE_0 16
#define SDX65_MASTER_QDSS_ETR 17
#define SDX65_MASTER_SDCC_1 18
#define SDX65_MASTER_USB3 19
#define SDX65_SLAVE_EBI1 512
#define SDX65_SLAVE_AOSS 513
#define SDX65_SLAVE_APPSS 514
#define SDX65_SLAVE_AUDIO 515
#define SDX65_SLAVE_BLSP_1 516
#define SDX65_SLAVE_CLK_CTL 517
#define SDX65_SLAVE_CRYPTO_0_CFG 518
#define SDX65_SLAVE_CNOC_DDRSS 519
#define SDX65_SLAVE_ECC_CFG 520
#define SDX65_SLAVE_IMEM_CFG 521
#define SDX65_SLAVE_IPA_CFG 522
#define SDX65_SLAVE_CNOC_MSS 523
#define SDX65_SLAVE_PCIE_PARF 524
#define SDX65_SLAVE_PDM 525
#define SDX65_SLAVE_PRNG 526
#define SDX65_SLAVE_QDSS_CFG 527
#define SDX65_SLAVE_QPIC 528
#define SDX65_SLAVE_SDCC_1 529
#define SDX65_SLAVE_SNOC_CFG 530
#define SDX65_SLAVE_SPMI_FETCHER 531
#define SDX65_SLAVE_SPMI_VGI_COEX 532
#define SDX65_SLAVE_TCSR 533
#define SDX65_SLAVE_TLMM 534
#define SDX65_SLAVE_USB3 535
#define SDX65_SLAVE_USB3_PHY_CFG 536
#define SDX65_SLAVE_ANOC_SNOC 537
#define SDX65_SLAVE_LLCC 538
#define SDX65_SLAVE_MEM_NOC_SNOC 539
#define SDX65_SLAVE_SNOC_MEM_NOC_GC 540
#define SDX65_SLAVE_MEM_NOC_PCIE_SNOC 541
#define SDX65_SLAVE_IMEM 542
#define SDX65_SLAVE_SERVICE_SNOC 543
#define SDX65_SLAVE_PCIE_0 544
#define SDX65_SLAVE_QDSS_STM 545
#define SDX65_SLAVE_TCU 546
#endif

395
drivers/interconnect/qcom/sdx75.c
View File

@@ -14,782 +14,724 @@
#include "bcm-voter.h"
#include "icc-common.h"
#include "icc-rpmh.h"
#include "sdx75.h"
static struct qcom_icc_node qpic_core_master = {
.name = "qpic_core_master",
.id = SDX75_MASTER_QPIC_CORE,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_SLAVE_QPIC_CORE },
};
static struct qcom_icc_node qup0_core_master;
static struct qcom_icc_node qnm_cnoc;
static struct qcom_icc_node alm_sys_tcu;
static struct qcom_icc_node chm_apps;
static struct qcom_icc_node qnm_gemnoc_cfg;
static struct qcom_icc_node qnm_mdsp;
static struct qcom_icc_node qnm_pcie;
static struct qcom_icc_node qnm_snoc_sf;
static struct qcom_icc_node xm_gic;
static struct qcom_icc_node xm_ipa2pcie;
static struct qcom_icc_node llcc_mc;
static struct qcom_icc_node xm_pcie3_0;
static struct qcom_icc_node xm_pcie3_1;
static struct qcom_icc_node xm_pcie3_2;
static struct qcom_icc_node qhm_audio;
static struct qcom_icc_node qhm_gic;
static struct qcom_icc_node qhm_pcie_rscc;
static struct qcom_icc_node qhm_qdss_bam;
static struct qcom_icc_node qhm_qpic;
static struct qcom_icc_node qhm_qup0;
static struct qcom_icc_node qnm_aggre_noc;
static struct qcom_icc_node qnm_gemnoc_cnoc;
static struct qcom_icc_node qnm_gemnoc_pcie;
static struct qcom_icc_node qnm_system_noc_cfg;
static struct qcom_icc_node qnm_system_noc_pcie_cfg;
static struct qcom_icc_node qxm_crypto;
static struct qcom_icc_node qxm_ipa;
static struct qcom_icc_node qxm_mvmss;
static struct qcom_icc_node xm_emac_0;
static struct qcom_icc_node xm_emac_1;
static struct qcom_icc_node xm_qdss_etr0;
static struct qcom_icc_node xm_qdss_etr1;
static struct qcom_icc_node xm_sdc1;
static struct qcom_icc_node xm_sdc4;
static struct qcom_icc_node xm_usb3;
static struct qcom_icc_node qup0_core_slave;
static struct qcom_icc_node qhs_lagg;
static struct qcom_icc_node qhs_mccc_master;
static struct qcom_icc_node qns_gemnoc;
static struct qcom_icc_node qss_snoop_bwmon;
static struct qcom_icc_node qns_gemnoc_cnoc;
static struct qcom_icc_node qns_llcc;
static struct qcom_icc_node qns_pcie;
static struct qcom_icc_node srvc_gemnoc;
static struct qcom_icc_node ebi;
static struct qcom_icc_node qns_pcie_gemnoc;
static struct qcom_icc_node ps_eth0_cfg;
static struct qcom_icc_node ps_eth1_cfg;
static struct qcom_icc_node qhs_audio;
static struct qcom_icc_node qhs_clk_ctl;
static struct qcom_icc_node qhs_crypto_cfg;
static struct qcom_icc_node qhs_imem_cfg;
static struct qcom_icc_node qhs_ipa;
static struct qcom_icc_node qhs_ipc_router;
static struct qcom_icc_node qhs_mss_cfg;
static struct qcom_icc_node qhs_mvmss_cfg;
static struct qcom_icc_node qhs_pcie0_cfg;
static struct qcom_icc_node qhs_pcie1_cfg;
static struct qcom_icc_node qhs_pcie2_cfg;
static struct qcom_icc_node qhs_pcie_rscc;
static struct qcom_icc_node qhs_pdm;
static struct qcom_icc_node qhs_prng;
static struct qcom_icc_node qhs_qdss_cfg;
static struct qcom_icc_node qhs_qpic;
static struct qcom_icc_node qhs_qup0;
static struct qcom_icc_node qhs_sdc1;
static struct qcom_icc_node qhs_sdc4;
static struct qcom_icc_node qhs_spmi_vgi_coex;
static struct qcom_icc_node qhs_tcsr;
static struct qcom_icc_node qhs_tlmm;
static struct qcom_icc_node qhs_usb3;
static struct qcom_icc_node qhs_usb3_phy;
static struct qcom_icc_node qns_a1noc;
static struct qcom_icc_node qns_ddrss_cfg;
static struct qcom_icc_node qns_gemnoc_sf;
static struct qcom_icc_node qns_system_noc_cfg;
static struct qcom_icc_node qns_system_noc_pcie_cfg;
static struct qcom_icc_node qxs_imem;
static struct qcom_icc_node srvc_pcie_system_noc;
static struct qcom_icc_node srvc_system_noc;
static struct qcom_icc_node xs_pcie_0;
static struct qcom_icc_node xs_pcie_1;
static struct qcom_icc_node xs_pcie_2;
static struct qcom_icc_node xs_qdss_stm;
static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
.id = SDX75_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_SLAVE_QUP_CORE_0 },
.link_nodes = { &qup0_core_slave },
};
static struct qcom_icc_node qnm_cnoc = {
.name = "qnm_cnoc",
.id = SDX75_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
.num_links = 4,
.links = { SDX75_SLAVE_LAGG_CFG, SDX75_SLAVE_MCCC_MASTER,
SDX75_SLAVE_GEM_NOC_CFG, SDX75_SLAVE_SNOOP_BWMON },
.link_nodes = { &qhs_lagg, &qhs_mccc_master,
&qns_gemnoc, &qss_snoop_bwmon },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
.id = SDX75_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
.num_links = 2,
.links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC },
.link_nodes = { &qns_gemnoc_cnoc, &qns_llcc },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
.id = SDX75_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 16,
.num_links = 3,
.links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC,
SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
.link_nodes = { &qns_gemnoc_cnoc, &qns_llcc,
&qns_pcie },
};
static struct qcom_icc_node qnm_gemnoc_cfg = {
.name = "qnm_gemnoc_cfg",
.id = SDX75_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_SLAVE_SERVICE_GEM_NOC },
.link_nodes = { &srvc_gemnoc },
};
static struct qcom_icc_node qnm_mdsp = {
.name = "qnm_mdsp",
.id = SDX75_MASTER_MSS_PROC,
.channels = 1,
.buswidth = 16,
.num_links = 3,
.links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC,
SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
.link_nodes = { &qns_gemnoc_cnoc, &qns_llcc,
&qns_pcie },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
.id = SDX75_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 2,
.links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC },
.link_nodes = { &qns_gemnoc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
.id = SDX75_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 3,
.links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC,
SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
.link_nodes = { &qns_gemnoc_cnoc, &qns_llcc,
&qns_pcie },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
.id = SDX75_MASTER_GIC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_LLCC },
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_node xm_ipa2pcie = {
.name = "xm_ipa2pcie",
.id = SDX75_MASTER_IPA_PCIE,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
.link_nodes = { &qns_pcie },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
.id = SDX75_MASTER_LLCC,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_SLAVE_EBI1 },
.link_nodes = { &ebi },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
.id = SDX75_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC },
.link_nodes = { &qns_pcie_gemnoc },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
.id = SDX75_MASTER_PCIE_1,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC },
.link_nodes = { &qns_pcie_gemnoc },
};
static struct qcom_icc_node xm_pcie3_2 = {
.name = "xm_pcie3_2",
.id = SDX75_MASTER_PCIE_2,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC },
.link_nodes = { &qns_pcie_gemnoc },
};
static struct qcom_icc_node qhm_audio = {
.name = "qhm_audio",
.id = SDX75_MASTER_AUDIO,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
.id = SDX75_MASTER_GIC_AHB,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qhm_pcie_rscc = {
.name = "qhm_pcie_rscc",
.id = SDX75_MASTER_PCIE_RSCC,
.channels = 1,
.buswidth = 4,
.num_links = 31,
.links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG,
SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL,
SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG,
SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG,
SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG,
SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG,
SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PDM,
SDX75_SLAVE_PRNG, SDX75_SLAVE_QDSS_CFG,
SDX75_SLAVE_QPIC, SDX75_SLAVE_QUP_0,
SDX75_SLAVE_SDCC_1, SDX75_SLAVE_SDCC_4,
SDX75_SLAVE_SPMI_VGI_COEX, SDX75_SLAVE_TCSR,
SDX75_SLAVE_TLMM, SDX75_SLAVE_USB3,
SDX75_SLAVE_USB3_PHY_CFG, SDX75_SLAVE_DDRSS_CFG,
SDX75_SLAVE_SNOC_CFG, SDX75_SLAVE_PCIE_ANOC_CFG,
SDX75_SLAVE_IMEM, SDX75_SLAVE_QDSS_STM,
SDX75_SLAVE_TCU },
.link_nodes = { &ps_eth0_cfg, &ps_eth1_cfg,
&qhs_audio, &qhs_clk_ctl,
&qhs_crypto_cfg, &qhs_imem_cfg,
&qhs_ipa, &qhs_ipc_router,
&qhs_mss_cfg, &qhs_mvmss_cfg,
&qhs_pcie0_cfg, &qhs_pcie1_cfg,
&qhs_pcie2_cfg, &qhs_pdm,
&qhs_prng, &qhs_qdss_cfg,
&qhs_qpic, &qhs_qup0,
&qhs_sdc1, &qhs_sdc4,
&qhs_spmi_vgi_coex, &qhs_tcsr,
&qhs_tlmm, &qhs_usb3,
&qhs_usb3_phy, &qns_ddrss_cfg,
&qns_system_noc_cfg, &qns_system_noc_pcie_cfg,
&qxs_imem, &xs_qdss_stm,
&xs_sys_tcu_cfg },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.id = SDX75_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_SLAVE_A1NOC_CFG },
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
.id = SDX75_MASTER_QPIC,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_SLAVE_A1NOC_CFG },
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
.id = SDX75_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_SLAVE_A1NOC_CFG },
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qnm_aggre_noc = {
.name = "qnm_aggre_noc",
.id = SDX75_MASTER_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
.id = SDX75_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 8,
.num_links = 32,
.links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG,
SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL,
SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG,
SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG,
SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG,
SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG,
SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PCIE_RSC_CFG,
SDX75_SLAVE_PDM, SDX75_SLAVE_PRNG,
SDX75_SLAVE_QDSS_CFG, SDX75_SLAVE_QPIC,
SDX75_SLAVE_QUP_0, SDX75_SLAVE_SDCC_1,
SDX75_SLAVE_SDCC_4, SDX75_SLAVE_SPMI_VGI_COEX,
SDX75_SLAVE_TCSR, SDX75_SLAVE_TLMM,
SDX75_SLAVE_USB3, SDX75_SLAVE_USB3_PHY_CFG,
SDX75_SLAVE_DDRSS_CFG, SDX75_SLAVE_SNOC_CFG,
SDX75_SLAVE_PCIE_ANOC_CFG, SDX75_SLAVE_IMEM,
SDX75_SLAVE_QDSS_STM, SDX75_SLAVE_TCU },
.link_nodes = { &ps_eth0_cfg, &ps_eth1_cfg,
&qhs_audio, &qhs_clk_ctl,
&qhs_crypto_cfg, &qhs_imem_cfg,
&qhs_ipa, &qhs_ipc_router,
&qhs_mss_cfg, &qhs_mvmss_cfg,
&qhs_pcie0_cfg, &qhs_pcie1_cfg,
&qhs_pcie2_cfg, &qhs_pcie_rscc,
&qhs_pdm, &qhs_prng,
&qhs_qdss_cfg, &qhs_qpic,
&qhs_qup0, &qhs_sdc1,
&qhs_sdc4, &qhs_spmi_vgi_coex,
&qhs_tcsr, &qhs_tlmm,
&qhs_usb3, &qhs_usb3_phy,
&qns_ddrss_cfg, &qns_system_noc_cfg,
&qns_system_noc_pcie_cfg, &qxs_imem,
&xs_qdss_stm, &xs_sys_tcu_cfg },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
.id = SDX75_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 3,
.links = { SDX75_SLAVE_PCIE_0, SDX75_SLAVE_PCIE_1,
SDX75_SLAVE_PCIE_2 },
.link_nodes = { &xs_pcie_0, &xs_pcie_1,
&xs_pcie_2 },
};
static struct qcom_icc_node qnm_system_noc_cfg = {
.name = "qnm_system_noc_cfg",
.id = SDX75_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_SLAVE_SERVICE_SNOC },
.link_nodes = { &srvc_system_noc },
};
static struct qcom_icc_node qnm_system_noc_pcie_cfg = {
.name = "qnm_system_noc_pcie_cfg",
.id = SDX75_MASTER_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_SLAVE_SERVICE_PCIE_ANOC },
.link_nodes = { &srvc_pcie_system_noc },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
.id = SDX75_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_A1NOC_CFG },
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
.id = SDX75_MASTER_IPA,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qxm_mvmss = {
.name = "qxm_mvmss",
.id = SDX75_MASTER_MVMSS,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_A1NOC_CFG },
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_emac_0 = {
.name = "xm_emac_0",
.id = SDX75_MASTER_EMAC_0,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_A1NOC_CFG },
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_emac_1 = {
.name = "xm_emac_1",
.id = SDX75_MASTER_EMAC_1,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_A1NOC_CFG },
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_qdss_etr0 = {
.name = "xm_qdss_etr0",
.id = SDX75_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_A1NOC_CFG },
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_qdss_etr1 = {
.name = "xm_qdss_etr1",
.id = SDX75_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_A1NOC_CFG },
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
.id = SDX75_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_A1NOC_CFG },
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
.id = SDX75_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_A1NOC_CFG },
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_usb3 = {
.name = "xm_usb3",
.id = SDX75_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_SLAVE_A1NOC_CFG },
};
static struct qcom_icc_node qpic_core_slave = {
.name = "qpic_core_slave",
.id = SDX75_SLAVE_QPIC_CORE,
.channels = 1,
.buswidth = 4,
.num_links = 0,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
.id = SDX75_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_lagg = {
.name = "qhs_lagg",
.id = SDX75_SLAVE_LAGG_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_mccc_master = {
.name = "qhs_mccc_master",
.id = SDX75_SLAVE_MCCC_MASTER,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_gemnoc = {
.name = "qns_gemnoc",
.id = SDX75_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qss_snoop_bwmon = {
.name = "qss_snoop_bwmon",
.id = SDX75_SLAVE_SNOOP_BWMON,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_gemnoc_cnoc = {
.name = "qns_gemnoc_cnoc",
.id = SDX75_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_MASTER_GEM_NOC_CNOC },
.link_nodes = { &qnm_gemnoc_cnoc },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
.id = SDX75_SLAVE_LLCC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SDX75_MASTER_LLCC },
.link_nodes = { &llcc_mc },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
.id = SDX75_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SDX75_MASTER_GEM_NOC_PCIE_SNOC },
.link_nodes = { &qnm_gemnoc_pcie },
};
static struct qcom_icc_node srvc_gemnoc = {
.name = "srvc_gemnoc",
.id = SDX75_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node ebi = {
.name = "ebi",
.id = SDX75_SLAVE_EBI1,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_pcie_gemnoc = {
.name = "qns_pcie_gemnoc",
.id = SDX75_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SDX75_MASTER_ANOC_PCIE_GEM_NOC },
.link_nodes = { &qnm_pcie },
};
static struct qcom_icc_node ps_eth0_cfg = {
.name = "ps_eth0_cfg",
.id = SDX75_SLAVE_ETH0_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node ps_eth1_cfg = {
.name = "ps_eth1_cfg",
.id = SDX75_SLAVE_ETH1_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_audio = {
.name = "qhs_audio",
.id = SDX75_SLAVE_AUDIO,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
.id = SDX75_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_crypto_cfg = {
.name = "qhs_crypto_cfg",
.id = SDX75_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
.id = SDX75_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
.id = SDX75_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
.id = SDX75_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
.id = SDX75_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_mvmss_cfg = {
.name = "qhs_mvmss_cfg",
.id = SDX75_SLAVE_ICBDI_MVMSS_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
.id = SDX75_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
.id = SDX75_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pcie2_cfg = {
.name = "qhs_pcie2_cfg",
.id = SDX75_SLAVE_PCIE_2_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pcie_rscc = {
.name = "qhs_pcie_rscc",
.id = SDX75_SLAVE_PCIE_RSC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
.id = SDX75_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
.id = SDX75_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
.id = SDX75_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qpic = {
.name = "qhs_qpic",
.id = SDX75_SLAVE_QPIC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
.id = SDX75_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
.id = SDX75_SLAVE_SDCC_1,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
.id = SDX75_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_spmi_vgi_coex = {
.name = "qhs_spmi_vgi_coex",
.id = SDX75_SLAVE_SPMI_VGI_COEX,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
.id = SDX75_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
.id = SDX75_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
.id = SDX75_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_usb3_phy = {
.name = "qhs_usb3_phy",
.id = SDX75_SLAVE_USB3_PHY_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_a1noc = {
.name = "qns_a1noc",
.id = SDX75_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX75_MASTER_ANOC_SNOC },
.link_nodes = { &qnm_aggre_noc },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
.id = SDX75_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_MASTER_CNOC_DC_NOC },
.link_nodes = { &qnm_cnoc },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
.id = SDX75_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SDX75_MASTER_SNOC_SF_MEM_NOC },
.link_nodes = { &qnm_snoc_sf },
};
static struct qcom_icc_node qns_system_noc_cfg = {
.name = "qns_system_noc_cfg",
.id = SDX75_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_MASTER_SNOC_CFG },
.link_nodes = { &qnm_system_noc_cfg },
};
static struct qcom_icc_node qns_system_noc_pcie_cfg = {
.name = "qns_system_noc_pcie_cfg",
.id = SDX75_SLAVE_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_MASTER_PCIE_ANOC_CFG },
.link_nodes = { &qnm_system_noc_pcie_cfg },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
.id = SDX75_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node srvc_pcie_system_noc = {
.name = "srvc_pcie_system_noc",
.id = SDX75_SLAVE_SERVICE_PCIE_ANOC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node srvc_system_noc = {
.name = "srvc_system_noc",
.id = SDX75_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
.id = SDX75_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
.id = SDX75_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node xs_pcie_2 = {
.name = "xs_pcie_2",
.id = SDX75_SLAVE_PCIE_2,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
.id = SDX75_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
.id = SDX75_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_bcm bcm_ce0 = {
@@ -831,12 +773,6 @@ static struct qcom_icc_bcm bcm_mc0 = {
.nodes = { &ebi },
};
static struct qcom_icc_bcm bcm_qp0 = {
.name = "QP0",
.num_nodes = 1,
.nodes = { &qpic_core_slave },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = true,
@@ -898,14 +834,11 @@ static struct qcom_icc_bcm bcm_sn4 = {
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
&bcm_qp0,
&bcm_qup0,
};
static struct qcom_icc_node * const clk_virt_nodes[] = {
[MASTER_QPIC_CORE] = &qpic_core_master,
[MASTER_QUP_CORE_0] = &qup0_core_master,
[SLAVE_QPIC_CORE] = &qpic_core_slave,
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
};

97
drivers/interconnect/qcom/sdx75.h
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@@ -1,97 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX75_H
#define __DRIVERS_INTERCONNECT_QCOM_SDX75_H
#define SDX75_MASTER_ANOC_PCIE_GEM_NOC 0
#define SDX75_MASTER_ANOC_SNOC 1
#define SDX75_MASTER_APPSS_PROC 2
#define SDX75_MASTER_AUDIO 3
#define SDX75_MASTER_CNOC_DC_NOC 4
#define SDX75_MASTER_CRYPTO 5
#define SDX75_MASTER_EMAC_0 6
#define SDX75_MASTER_EMAC_1 7
#define SDX75_MASTER_GEM_NOC_CFG 8
#define SDX75_MASTER_GEM_NOC_CNOC 9
#define SDX75_MASTER_GEM_NOC_PCIE_SNOC 10
#define SDX75_MASTER_GIC 11
#define SDX75_MASTER_GIC_AHB 12
#define SDX75_MASTER_IPA 13
#define SDX75_MASTER_IPA_PCIE 14
#define SDX75_MASTER_LLCC 15
#define SDX75_MASTER_MSS_PROC 16
#define SDX75_MASTER_MVMSS 17
#define SDX75_MASTER_PCIE_0 18
#define SDX75_MASTER_PCIE_1 19
#define SDX75_MASTER_PCIE_2 20
#define SDX75_MASTER_PCIE_ANOC_CFG 21
#define SDX75_MASTER_PCIE_RSCC 22
#define SDX75_MASTER_QDSS_BAM 23
#define SDX75_MASTER_QDSS_ETR 24
#define SDX75_MASTER_QDSS_ETR_1 25
#define SDX75_MASTER_QPIC 26
#define SDX75_MASTER_QPIC_CORE 27
#define SDX75_MASTER_QUP_0 28
#define SDX75_MASTER_QUP_CORE_0 29
#define SDX75_MASTER_SDCC_1 30
#define SDX75_MASTER_SDCC_4 31
#define SDX75_MASTER_SNOC_CFG 32
#define SDX75_MASTER_SNOC_SF_MEM_NOC 33
#define SDX75_MASTER_SYS_TCU 34
#define SDX75_MASTER_USB3_0 35
#define SDX75_SLAVE_A1NOC_CFG 36
#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 37
#define SDX75_SLAVE_AUDIO 38
#define SDX75_SLAVE_CLK_CTL 39
#define SDX75_SLAVE_CRYPTO_0_CFG 40
#define SDX75_SLAVE_CNOC_MSS 41
#define SDX75_SLAVE_DDRSS_CFG 42
#define SDX75_SLAVE_EBI1 43
#define SDX75_SLAVE_ETH0_CFG 44
#define SDX75_SLAVE_ETH1_CFG 45
#define SDX75_SLAVE_GEM_NOC_CFG 46
#define SDX75_SLAVE_GEM_NOC_CNOC 47
#define SDX75_SLAVE_ICBDI_MVMSS_CFG 48
#define SDX75_SLAVE_IMEM 49
#define SDX75_SLAVE_IMEM_CFG 50
#define SDX75_SLAVE_IPA_CFG 51
#define SDX75_SLAVE_IPC_ROUTER_CFG 52
#define SDX75_SLAVE_LAGG_CFG 53
#define SDX75_SLAVE_LLCC 54
#define SDX75_SLAVE_MCCC_MASTER 55
#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 56
#define SDX75_SLAVE_PCIE_0 57
#define SDX75_SLAVE_PCIE_1 58
#define SDX75_SLAVE_PCIE_2 59
#define SDX75_SLAVE_PCIE_0_CFG 60
#define SDX75_SLAVE_PCIE_1_CFG 61
#define SDX75_SLAVE_PCIE_2_CFG 62
#define SDX75_SLAVE_PCIE_ANOC_CFG 63
#define SDX75_SLAVE_PCIE_RSC_CFG 64
#define SDX75_SLAVE_PDM 65
#define SDX75_SLAVE_PRNG 66
#define SDX75_SLAVE_QDSS_CFG 67
#define SDX75_SLAVE_QDSS_STM 68
#define SDX75_SLAVE_QPIC 69
#define SDX75_SLAVE_QPIC_CORE 70
#define SDX75_SLAVE_QUP_0 71
#define SDX75_SLAVE_QUP_CORE_0 72
#define SDX75_SLAVE_SDCC_1 73
#define SDX75_SLAVE_SDCC_4 74
#define SDX75_SLAVE_SERVICE_GEM_NOC 75
#define SDX75_SLAVE_SERVICE_PCIE_ANOC 76
#define SDX75_SLAVE_SERVICE_SNOC 77
#define SDX75_SLAVE_SNOC_CFG 78
#define SDX75_SLAVE_SNOC_GEM_NOC_SF 79
#define SDX75_SLAVE_SNOOP_BWMON 80
#define SDX75_SLAVE_SPMI_VGI_COEX 81
#define SDX75_SLAVE_TCSR 82
#define SDX75_SLAVE_TCU 83
#define SDX75_SLAVE_TLMM 84
#define SDX75_SLAVE_USB3 85
#define SDX75_SLAVE_USB3_PHY_CFG 86
#endif

927
drivers/interconnect/qcom/sm6350.c
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File diff suppressed because it is too large Load Diff

139
drivers/interconnect/qcom/sm6350.h
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@@ -1,139 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm #define SM6350 interconnect IDs
*
* Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com>
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM6350_H
#define __DRIVERS_INTERCONNECT_QCOM_SM6350_H
#define SM6350_A1NOC_SNOC_MAS 0
#define SM6350_A1NOC_SNOC_SLV 1
#define SM6350_A2NOC_SNOC_MAS 2
#define SM6350_A2NOC_SNOC_SLV 3
#define SM6350_MASTER_A1NOC_CFG 4
#define SM6350_MASTER_A2NOC_CFG 5
#define SM6350_MASTER_AMPSS_M0 6
#define SM6350_MASTER_CAMNOC_HF 7
#define SM6350_MASTER_CAMNOC_HF0_UNCOMP 8
#define SM6350_MASTER_CAMNOC_ICP 9
#define SM6350_MASTER_CAMNOC_ICP_UNCOMP 10
#define SM6350_MASTER_CAMNOC_SF 11
#define SM6350_MASTER_CAMNOC_SF_UNCOMP 12
#define SM6350_MASTER_CNOC_DC_NOC 13
#define SM6350_MASTER_CNOC_MNOC_CFG 14
#define SM6350_MASTER_COMPUTE_NOC 15
#define SM6350_MASTER_CRYPTO_CORE_0 16
#define SM6350_MASTER_EMMC 17
#define SM6350_MASTER_GEM_NOC_CFG 18
#define SM6350_MASTER_GEM_NOC_SNOC 19
#define SM6350_MASTER_GIC 20
#define SM6350_MASTER_GRAPHICS_3D 21
#define SM6350_MASTER_IPA 22
#define SM6350_MASTER_LLCC 23
#define SM6350_MASTER_MDP_PORT0 24
#define SM6350_MASTER_MNOC_HF_MEM_NOC 25
#define SM6350_MASTER_MNOC_SF_MEM_NOC 26
#define SM6350_MASTER_NPU 27
#define SM6350_MASTER_NPU_NOC_CFG 28
#define SM6350_MASTER_NPU_PROC 29
#define SM6350_MASTER_NPU_SYS 30
#define SM6350_MASTER_PIMEM 31
#define SM6350_MASTER_QDSS_BAM 32
#define SM6350_MASTER_QDSS_DAP 33
#define SM6350_MASTER_QDSS_ETR 34
#define SM6350_MASTER_QUP_0 35
#define SM6350_MASTER_QUP_1 36
#define SM6350_MASTER_QUP_CORE_0 37
#define SM6350_MASTER_QUP_CORE_1 38
#define SM6350_MASTER_SDCC_2 39
#define SM6350_MASTER_SNOC_CFG 40
#define SM6350_MASTER_SNOC_GC_MEM_NOC 41
#define SM6350_MASTER_SNOC_SF_MEM_NOC 42
#define SM6350_MASTER_SYS_TCU 43
#define SM6350_MASTER_UFS_MEM 44
#define SM6350_MASTER_USB3 45
#define SM6350_MASTER_VIDEO_P0 46
#define SM6350_MASTER_VIDEO_PROC 47
#define SM6350_SLAVE_A1NOC_CFG 48
#define SM6350_SLAVE_A2NOC_CFG 49
#define SM6350_SLAVE_AHB2PHY 50
#define SM6350_SLAVE_AHB2PHY_2 51
#define SM6350_SLAVE_AOSS 52
#define SM6350_SLAVE_APPSS 53
#define SM6350_SLAVE_BOOT_ROM 54
#define SM6350_SLAVE_CAMERA_CFG 55
#define SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG 56
#define SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG 57
#define SM6350_SLAVE_CAMNOC_UNCOMP 58
#define SM6350_SLAVE_CDSP_GEM_NOC 59
#define SM6350_SLAVE_CLK_CTL 60
#define SM6350_SLAVE_CNOC_DDRSS 61
#define SM6350_SLAVE_CNOC_MNOC_CFG 62
#define SM6350_SLAVE_CNOC_MSS 63
#define SM6350_SLAVE_CRYPTO_0_CFG 64
#define SM6350_SLAVE_DCC_CFG 65
#define SM6350_SLAVE_DISPLAY_CFG 66
#define SM6350_SLAVE_DISPLAY_THROTTLE_CFG 67
#define SM6350_SLAVE_EBI_CH0 68
#define SM6350_SLAVE_EMMC_CFG 69
#define SM6350_SLAVE_GEM_NOC_CFG 70
#define SM6350_SLAVE_GEM_NOC_SNOC 71
#define SM6350_SLAVE_GLM 72
#define SM6350_SLAVE_GRAPHICS_3D_CFG 73
#define SM6350_SLAVE_IMEM_CFG 74
#define SM6350_SLAVE_IPA_CFG 75
#define SM6350_SLAVE_ISENSE_CFG 76
#define SM6350_SLAVE_LLCC 77
#define SM6350_SLAVE_LLCC_CFG 78
#define SM6350_SLAVE_MCDMA_MS_MPU_CFG 79
#define SM6350_SLAVE_MNOC_HF_MEM_NOC 80
#define SM6350_SLAVE_MNOC_SF_MEM_NOC 81
#define SM6350_SLAVE_MSS_PROC_MS_MPU_CFG 82
#define SM6350_SLAVE_NPU_CAL_DP0 83
#define SM6350_SLAVE_NPU_CFG 84
#define SM6350_SLAVE_NPU_COMPUTE_NOC 85
#define SM6350_SLAVE_NPU_CP 86
#define SM6350_SLAVE_NPU_DPM 87
#define SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG 88
#define SM6350_SLAVE_NPU_LLM_CFG 89
#define SM6350_SLAVE_NPU_TCM 90
#define SM6350_SLAVE_OCIMEM 91
#define SM6350_SLAVE_PDM 92
#define SM6350_SLAVE_PIMEM 93
#define SM6350_SLAVE_PIMEM_CFG 94
#define SM6350_SLAVE_PRNG 95
#define SM6350_SLAVE_QDSS_CFG 96
#define SM6350_SLAVE_QDSS_STM 97
#define SM6350_SLAVE_QM_CFG 98
#define SM6350_SLAVE_QM_MPU_CFG 99
#define SM6350_SLAVE_QUP_0 100
#define SM6350_SLAVE_QUP_1 101
#define SM6350_SLAVE_QUP_CORE_0 102
#define SM6350_SLAVE_QUP_CORE_1 103
#define SM6350_SLAVE_RBCPR_CX_CFG 104
#define SM6350_SLAVE_RBCPR_MX_CFG 105
#define SM6350_SLAVE_SDCC_2 106
#define SM6350_SLAVE_SECURITY 107
#define SM6350_SLAVE_SERVICE_A1NOC 108
#define SM6350_SLAVE_SERVICE_A2NOC 109
#define SM6350_SLAVE_SERVICE_CNOC 110
#define SM6350_SLAVE_SERVICE_GEM_NOC 111
#define SM6350_SLAVE_SERVICE_MNOC 112
#define SM6350_SLAVE_SERVICE_NPU_NOC 113
#define SM6350_SLAVE_SERVICE_SNOC 114
#define SM6350_SLAVE_SNOC_CFG 115
#define SM6350_SLAVE_SNOC_GEM_NOC_GC 116
#define SM6350_SLAVE_SNOC_GEM_NOC_SF 117
#define SM6350_SLAVE_TCSR 118
#define SM6350_SLAVE_TCU 119
#define SM6350_SLAVE_UFS_MEM_CFG 120
#define SM6350_SLAVE_USB3 121
#define SM6350_SLAVE_VENUS_CFG 122
#define SM6350_SLAVE_VENUS_THROTTLE_CFG 123
#define SM6350_SLAVE_VSENSE_CTRL_CFG 124
#define SM6350_SNOC_CNOC_MAS 125
#define SM6350_SNOC_CNOC_SLV 126
#endif

653
drivers/interconnect/qcom/sm7150.c
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drivers/interconnect/qcom/sm7150.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Qualcomm #define SM7150 interconnect IDs
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM7150_H
#define __DRIVERS_INTERCONNECT_QCOM_SM7150_H
#define SM7150_A1NOC_SNOC_MAS 0
#define SM7150_A1NOC_SNOC_SLV 1
#define SM7150_A2NOC_SNOC_MAS 2
#define SM7150_A2NOC_SNOC_SLV 3
#define SM7150_MASTER_A1NOC_CFG 4
#define SM7150_MASTER_A2NOC_CFG 5
#define SM7150_MASTER_AMPSS_M0 6
#define SM7150_MASTER_CAMNOC_HF0 7
#define SM7150_MASTER_CAMNOC_HF0_UNCOMP 8
#define SM7150_MASTER_CAMNOC_NRT 9
#define SM7150_MASTER_CAMNOC_NRT_UNCOMP 10
#define SM7150_MASTER_CAMNOC_RT 11
#define SM7150_MASTER_CAMNOC_RT_UNCOMP 12
#define SM7150_MASTER_CAMNOC_SF 13
#define SM7150_MASTER_CAMNOC_SF_UNCOMP 14
#define SM7150_MASTER_CNOC_A2NOC 15
#define SM7150_MASTER_CNOC_DC_NOC 16
#define SM7150_MASTER_CNOC_MNOC_CFG 17
#define SM7150_MASTER_COMPUTE_NOC 18
#define SM7150_MASTER_CRYPTO_CORE_0 19
#define SM7150_MASTER_EMMC 20
#define SM7150_MASTER_GEM_NOC_CFG 21
#define SM7150_MASTER_GEM_NOC_PCIE_SNOC 22
#define SM7150_MASTER_GEM_NOC_SNOC 23
#define SM7150_MASTER_GIC 24
#define SM7150_MASTER_GRAPHICS_3D 25
#define SM7150_MASTER_IPA 26
#define SM7150_MASTER_LLCC 27
#define SM7150_MASTER_MDP_PORT0 28
#define SM7150_MASTER_MDP_PORT1 29
#define SM7150_MASTER_MNOC_HF_MEM_NOC 30
#define SM7150_MASTER_MNOC_SF_MEM_NOC 31
#define SM7150_MASTER_NPU 32
#define SM7150_MASTER_PCIE 33
#define SM7150_MASTER_PIMEM 34
#define SM7150_MASTER_QDSS_BAM 35
#define SM7150_MASTER_QDSS_DAP 36
#define SM7150_MASTER_QDSS_ETR 37
#define SM7150_MASTER_QUP_0 38
#define SM7150_MASTER_QUP_1 39
#define SM7150_MASTER_ROTATOR 40
#define SM7150_MASTER_SDCC_2 41
#define SM7150_MASTER_SDCC_4 42
#define SM7150_MASTER_SNOC_CFG 43
#define SM7150_MASTER_SNOC_GC_MEM_NOC 44
#define SM7150_MASTER_SNOC_SF_MEM_NOC 45
#define SM7150_MASTER_SPDM 46
#define SM7150_MASTER_SYS_TCU 47
#define SM7150_MASTER_TSIF 48
#define SM7150_MASTER_UFS_MEM 49
#define SM7150_MASTER_USB3 50
#define SM7150_MASTER_VIDEO_P0 51
#define SM7150_MASTER_VIDEO_P1 52
#define SM7150_MASTER_VIDEO_PROC 53
#define SM7150_SLAVE_A1NOC_CFG 54
#define SM7150_SLAVE_A2NOC_CFG 55
#define SM7150_SLAVE_AHB2PHY_NORTH 56
#define SM7150_SLAVE_AHB2PHY_SOUTH 57
#define SM7150_SLAVE_AHB2PHY_WEST 58
#define SM7150_SLAVE_ANOC_PCIE_GEM_NOC 59
#define SM7150_SLAVE_AOP 60
#define SM7150_SLAVE_AOSS 61
#define SM7150_SLAVE_APPSS 62
#define SM7150_SLAVE_CAMERA_CFG 63
#define SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG 64
#define SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG 65
#define SM7150_SLAVE_CAMNOC_UNCOMP 66
#define SM7150_SLAVE_CDSP_CFG 67
#define SM7150_SLAVE_CDSP_GEM_NOC 68
#define SM7150_SLAVE_CLK_CTL 69
#define SM7150_SLAVE_CNOC_A2NOC 70
#define SM7150_SLAVE_CNOC_DDRSS 71
#define SM7150_SLAVE_CNOC_MNOC_CFG 72
#define SM7150_SLAVE_CRYPTO_0_CFG 73
#define SM7150_SLAVE_DISPLAY_CFG 74
#define SM7150_SLAVE_DISPLAY_THROTTLE_CFG 75
#define SM7150_SLAVE_EBI_CH0 76
#define SM7150_SLAVE_EMMC_CFG 77
#define SM7150_SLAVE_GEM_NOC_CFG 78
#define SM7150_SLAVE_GEM_NOC_SNOC 79
#define SM7150_SLAVE_GLM 80
#define SM7150_SLAVE_GRAPHICS_3D_CFG 81
#define SM7150_SLAVE_IMEM_CFG 82
#define SM7150_SLAVE_IPA_CFG 83
#define SM7150_SLAVE_LLCC 84
#define SM7150_SLAVE_LLCC_CFG 85
#define SM7150_SLAVE_MNOC_HF_MEM_NOC 86
#define SM7150_SLAVE_MNOC_SF_MEM_NOC 87
#define SM7150_SLAVE_MSS_PROC_MS_MPU_CFG 88
#define SM7150_SLAVE_OCIMEM 89
#define SM7150_SLAVE_PCIE_CFG 90
#define SM7150_SLAVE_PDM 91
#define SM7150_SLAVE_PIMEM 92
#define SM7150_SLAVE_PIMEM_CFG 93
#define SM7150_SLAVE_PRNG 94
#define SM7150_SLAVE_QDSS_CFG 95
#define SM7150_SLAVE_QDSS_STM 96
#define SM7150_SLAVE_QUP_0 97
#define SM7150_SLAVE_QUP_1 98
#define SM7150_SLAVE_RBCPR_CX_CFG 99
#define SM7150_SLAVE_RBCPR_MX_CFG 100
#define SM7150_SLAVE_SDCC_2 101
#define SM7150_SLAVE_SDCC_4 102
#define SM7150_SLAVE_SERVICE_A1NOC 103
#define SM7150_SLAVE_SERVICE_A2NOC 104
#define SM7150_SLAVE_SERVICE_CNOC 105
#define SM7150_SLAVE_SERVICE_GEM_NOC 106
#define SM7150_SLAVE_SERVICE_MNOC 107
#define SM7150_SLAVE_SERVICE_SNOC 108
#define SM7150_SLAVE_SNOC_CFG 109
#define SM7150_SLAVE_SNOC_GEM_NOC_GC 110
#define SM7150_SLAVE_SNOC_GEM_NOC_SF 111
#define SM7150_SLAVE_SPDM_WRAPPER 112
#define SM7150_SLAVE_TCSR 113
#define SM7150_SLAVE_TCU 114
#define SM7150_SLAVE_TLMM_NORTH 115
#define SM7150_SLAVE_TLMM_SOUTH 116
#define SM7150_SLAVE_TLMM_WEST 117
#define SM7150_SLAVE_TSIF 118
#define SM7150_SLAVE_UFS_MEM_CFG 119
#define SM7150_SLAVE_USB3 120
#define SM7150_SLAVE_VENUS_CFG 121
#define SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG 122
#define SM7150_SLAVE_VENUS_THROTTLE_CFG 123
#define SM7150_SLAVE_VSENSE_CTRL_CFG 124
#define SM7150_SNOC_CNOC_MAS 125
#define SM7150_SNOC_CNOC_SLV 126
#endif

706
drivers/interconnect/qcom/sm8150.c
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drivers/interconnect/qcom/sm8150.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm #define SM8250 interconnect IDs
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8150_H
#define __DRIVERS_INTERCONNECT_QCOM_SM8150_H
#define SM8150_A1NOC_SNOC_MAS 0
#define SM8150_A1NOC_SNOC_SLV 1
#define SM8150_A2NOC_SNOC_MAS 2
#define SM8150_A2NOC_SNOC_SLV 3
#define SM8150_MASTER_A1NOC_CFG 4
#define SM8150_MASTER_A2NOC_CFG 5
#define SM8150_MASTER_AMPSS_M0 6
#define SM8150_MASTER_CAMNOC_HF0 7
#define SM8150_MASTER_CAMNOC_HF0_UNCOMP 8
#define SM8150_MASTER_CAMNOC_HF1 9
#define SM8150_MASTER_CAMNOC_HF1_UNCOMP 10
#define SM8150_MASTER_CAMNOC_SF 11
#define SM8150_MASTER_CAMNOC_SF_UNCOMP 12
#define SM8150_MASTER_CNOC_A2NOC 13
#define SM8150_MASTER_CNOC_DC_NOC 14
#define SM8150_MASTER_CNOC_MNOC_CFG 15
#define SM8150_MASTER_COMPUTE_NOC 16
#define SM8150_MASTER_CRYPTO_CORE_0 17
#define SM8150_MASTER_ECC 18
#define SM8150_MASTER_EMAC 19
#define SM8150_MASTER_GEM_NOC_CFG 20
#define SM8150_MASTER_GEM_NOC_PCIE_SNOC 21
#define SM8150_MASTER_GEM_NOC_SNOC 22
#define SM8150_MASTER_GIC 23
#define SM8150_MASTER_GPU_TCU 24
#define SM8150_MASTER_GRAPHICS_3D 25
#define SM8150_MASTER_IPA 26
/* 27 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SM8150_MASTER_LLCC 28
#define SM8150_MASTER_MDP_PORT0 29
#define SM8150_MASTER_MDP_PORT1 30
#define SM8150_MASTER_MNOC_HF_MEM_NOC 31
#define SM8150_MASTER_MNOC_SF_MEM_NOC 32
#define SM8150_MASTER_NPU 33
#define SM8150_MASTER_PCIE 34
#define SM8150_MASTER_PCIE_1 35
#define SM8150_MASTER_PIMEM 36
#define SM8150_MASTER_QDSS_BAM 37
#define SM8150_MASTER_QDSS_DAP 38
#define SM8150_MASTER_QDSS_ETR 39
#define SM8150_MASTER_QSPI 40
#define SM8150_MASTER_QUP_0 41
#define SM8150_MASTER_QUP_1 42
#define SM8150_MASTER_QUP_2 43
#define SM8150_MASTER_ROTATOR 44
#define SM8150_MASTER_SDCC_2 45
#define SM8150_MASTER_SDCC_4 46
#define SM8150_MASTER_SENSORS_AHB 47
#define SM8150_MASTER_SNOC_CFG 48
#define SM8150_MASTER_SNOC_GC_MEM_NOC 49
#define SM8150_MASTER_SNOC_SF_MEM_NOC 50
#define SM8150_MASTER_SPDM 51
#define SM8150_MASTER_SYS_TCU 52
#define SM8150_MASTER_TSIF 53
#define SM8150_MASTER_UFS_MEM 54
#define SM8150_MASTER_USB3 55
#define SM8150_MASTER_USB3_1 56
#define SM8150_MASTER_VIDEO_P0 57
#define SM8150_MASTER_VIDEO_P1 58
#define SM8150_MASTER_VIDEO_PROC 59
#define SM8150_SLAVE_A1NOC_CFG 60
#define SM8150_SLAVE_A2NOC_CFG 61
#define SM8150_SLAVE_AHB2PHY_SOUTH 62
#define SM8150_SLAVE_ANOC_PCIE_GEM_NOC 63
#define SM8150_SLAVE_AOP 64
#define SM8150_SLAVE_AOSS 65
#define SM8150_SLAVE_APPSS 66
#define SM8150_SLAVE_CAMERA_CFG 67
#define SM8150_SLAVE_CAMNOC_UNCOMP 68
#define SM8150_SLAVE_CDSP_CFG 69
#define SM8150_SLAVE_CDSP_MEM_NOC 70
#define SM8150_SLAVE_CLK_CTL 71
#define SM8150_SLAVE_CNOC_A2NOC 72
#define SM8150_SLAVE_CNOC_DDRSS 73
#define SM8150_SLAVE_CNOC_MNOC_CFG 74
#define SM8150_SLAVE_CRYPTO_0_CFG 75
#define SM8150_SLAVE_DISPLAY_CFG 76
#define SM8150_SLAVE_EBI_CH0 77
#define SM8150_SLAVE_ECC 78
#define SM8150_SLAVE_EMAC_CFG 79
#define SM8150_SLAVE_GEM_NOC_CFG 80
#define SM8150_SLAVE_GEM_NOC_SNOC 81
#define SM8150_SLAVE_GLM 82
#define SM8150_SLAVE_GRAPHICS_3D_CFG 83
#define SM8150_SLAVE_IMEM_CFG 84
#define SM8150_SLAVE_IPA_CFG 85
/* 86 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SM8150_SLAVE_LLCC 87
#define SM8150_SLAVE_LLCC_CFG 88
#define SM8150_SLAVE_MNOC_HF_MEM_NOC 89
#define SM8150_SLAVE_MNOC_SF_MEM_NOC 90
#define SM8150_SLAVE_MSS_PROC_MS_MPU_CFG 91
#define SM8150_SLAVE_NORTH_PHY_CFG 92
#define SM8150_SLAVE_NPU_CFG 93
#define SM8150_SLAVE_OCIMEM 94
#define SM8150_SLAVE_PCIE_0 95
#define SM8150_SLAVE_PCIE_0_CFG 96
#define SM8150_SLAVE_PCIE_1 97
#define SM8150_SLAVE_PCIE_1_CFG 98
#define SM8150_SLAVE_PIMEM 99
#define SM8150_SLAVE_PIMEM_CFG 100
#define SM8150_SLAVE_PRNG 101
#define SM8150_SLAVE_QDSS_CFG 102
#define SM8150_SLAVE_QDSS_STM 103
#define SM8150_SLAVE_QSPI 104
#define SM8150_SLAVE_QUP_0 105
#define SM8150_SLAVE_QUP_1 106
#define SM8150_SLAVE_QUP_2 107
#define SM8150_SLAVE_RBCPR_CX_CFG 108
#define SM8150_SLAVE_RBCPR_MMCX_CFG 109
#define SM8150_SLAVE_RBCPR_MX_CFG 110
#define SM8150_SLAVE_SDCC_2 111
#define SM8150_SLAVE_SDCC_4 112
#define SM8150_SLAVE_SERVICE_A1NOC 113
#define SM8150_SLAVE_SERVICE_A2NOC 114
#define SM8150_SLAVE_SERVICE_CNOC 115
#define SM8150_SLAVE_SERVICE_GEM_NOC 116
#define SM8150_SLAVE_SERVICE_MNOC 117
#define SM8150_SLAVE_SERVICE_SNOC 118
#define SM8150_SLAVE_SNOC_CFG 119
#define SM8150_SLAVE_SNOC_GEM_NOC_GC 120
#define SM8150_SLAVE_SNOC_GEM_NOC_SF 121
#define SM8150_SLAVE_SPDM_WRAPPER 122
#define SM8150_SLAVE_SPSS_CFG 123
#define SM8150_SLAVE_SSC_CFG 124
#define SM8150_SLAVE_TCSR 125
#define SM8150_SLAVE_TCU 126
#define SM8150_SLAVE_TLMM_EAST 127
#define SM8150_SLAVE_TLMM_NORTH 128
#define SM8150_SLAVE_TLMM_SOUTH 129
#define SM8150_SLAVE_TLMM_WEST 130
#define SM8150_SLAVE_TSIF 131
#define SM8150_SLAVE_UFS_CARD_CFG 132
#define SM8150_SLAVE_UFS_MEM_CFG 133
#define SM8150_SLAVE_USB3 134
#define SM8150_SLAVE_USB3_1 135
#define SM8150_SLAVE_VENUS_CFG 136
#define SM8150_SLAVE_VSENSE_CTRL_CFG 137
#define SM8150_SNOC_CNOC_MAS 138
#define SM8150_SNOC_CNOC_SLV 139
#endif

736
drivers/interconnect/qcom/sm8250.c
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drivers/interconnect/qcom/sm8250.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm #define SM8250 interconnect IDs
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8250_H
#define __DRIVERS_INTERCONNECT_QCOM_SM8250_H
#define SM8250_A1NOC_SNOC_MAS 0
#define SM8250_A1NOC_SNOC_SLV 1
#define SM8250_A2NOC_SNOC_MAS 2
#define SM8250_A2NOC_SNOC_SLV 3
#define SM8250_MASTER_A1NOC_CFG 4
#define SM8250_MASTER_A2NOC_CFG 5
#define SM8250_MASTER_AMPSS_M0 6
#define SM8250_MASTER_ANOC_PCIE_GEM_NOC 7
#define SM8250_MASTER_CAMNOC_HF 8
#define SM8250_MASTER_CAMNOC_ICP 9
#define SM8250_MASTER_CAMNOC_SF 10
#define SM8250_MASTER_CNOC_A2NOC 11
#define SM8250_MASTER_CNOC_DC_NOC 12
#define SM8250_MASTER_CNOC_MNOC_CFG 13
#define SM8250_MASTER_COMPUTE_NOC 14
#define SM8250_MASTER_CRYPTO_CORE_0 15
#define SM8250_MASTER_GEM_NOC_CFG 16
#define SM8250_MASTER_GEM_NOC_PCIE_SNOC 17
#define SM8250_MASTER_GEM_NOC_SNOC 18
#define SM8250_MASTER_GIC 19
#define SM8250_MASTER_GPU_TCU 20
#define SM8250_MASTER_GRAPHICS_3D 21
#define SM8250_MASTER_IPA 22
/* 23 was used by MASTER_IPA_CORE, now represented as RPMh clock */
#define SM8250_MASTER_LLCC 24
#define SM8250_MASTER_MDP_PORT0 25
#define SM8250_MASTER_MDP_PORT1 26
#define SM8250_MASTER_MNOC_HF_MEM_NOC 27
#define SM8250_MASTER_MNOC_SF_MEM_NOC 28
#define SM8250_MASTER_NPU 29
#define SM8250_MASTER_NPU_CDP 30
#define SM8250_MASTER_NPU_NOC_CFG 31
#define SM8250_MASTER_NPU_SYS 32
#define SM8250_MASTER_PCIE 33
#define SM8250_MASTER_PCIE_1 34
#define SM8250_MASTER_PCIE_2 35
#define SM8250_MASTER_PIMEM 36
#define SM8250_MASTER_QDSS_BAM 37
#define SM8250_MASTER_QDSS_DAP 38
#define SM8250_MASTER_QDSS_ETR 39
#define SM8250_MASTER_QSPI_0 40
#define SM8250_MASTER_QUP_0 41
#define SM8250_MASTER_QUP_1 42
#define SM8250_MASTER_QUP_2 43
#define SM8250_MASTER_ROTATOR 44
#define SM8250_MASTER_SDCC_2 45
#define SM8250_MASTER_SDCC_4 46
#define SM8250_MASTER_SNOC_CFG 47
#define SM8250_MASTER_SNOC_GC_MEM_NOC 48
#define SM8250_MASTER_SNOC_SF_MEM_NOC 49
#define SM8250_MASTER_SYS_TCU 50
#define SM8250_MASTER_TSIF 51
#define SM8250_MASTER_UFS_CARD 52
#define SM8250_MASTER_UFS_MEM 53
#define SM8250_MASTER_USB3 54
#define SM8250_MASTER_USB3_1 55
#define SM8250_MASTER_VIDEO_P0 56
#define SM8250_MASTER_VIDEO_P1 57
#define SM8250_MASTER_VIDEO_PROC 58
#define SM8250_SLAVE_A1NOC_CFG 59
#define SM8250_SLAVE_A2NOC_CFG 60
#define SM8250_SLAVE_AHB2PHY_NORTH 61
#define SM8250_SLAVE_AHB2PHY_SOUTH 62
#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC 63
#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 64
#define SM8250_SLAVE_AOSS 65
#define SM8250_SLAVE_APPSS 66
#define SM8250_SLAVE_CAMERA_CFG 67
#define SM8250_SLAVE_CDSP_CFG 68
#define SM8250_SLAVE_CDSP_MEM_NOC 69
#define SM8250_SLAVE_CLK_CTL 70
#define SM8250_SLAVE_CNOC_A2NOC 71
#define SM8250_SLAVE_CNOC_DDRSS 72
#define SM8250_SLAVE_CNOC_MNOC_CFG 73
#define SM8250_SLAVE_CRYPTO_0_CFG 74
#define SM8250_SLAVE_CX_RDPM 75
#define SM8250_SLAVE_DCC_CFG 76
#define SM8250_SLAVE_DISPLAY_CFG 77
#define SM8250_SLAVE_EBI_CH0 78
#define SM8250_SLAVE_GEM_NOC_CFG 79
#define SM8250_SLAVE_GEM_NOC_SNOC 80
#define SM8250_SLAVE_GRAPHICS_3D_CFG 81
#define SM8250_SLAVE_IMEM_CFG 82
#define SM8250_SLAVE_IPA_CFG 83
/* 84 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SM8250_SLAVE_IPC_ROUTER_CFG 85
#define SM8250_SLAVE_ISENSE_CFG 86
#define SM8250_SLAVE_LLCC 87
#define SM8250_SLAVE_LLCC_CFG 88
#define SM8250_SLAVE_LPASS 89
#define SM8250_SLAVE_MEM_NOC_PCIE_SNOC 90
#define SM8250_SLAVE_MNOC_HF_MEM_NOC 91
#define SM8250_SLAVE_MNOC_SF_MEM_NOC 92
#define SM8250_SLAVE_NPU_CAL_DP0 93
#define SM8250_SLAVE_NPU_CAL_DP1 94
#define SM8250_SLAVE_NPU_CFG 95
#define SM8250_SLAVE_NPU_COMPUTE_NOC 96
#define SM8250_SLAVE_NPU_CP 97
#define SM8250_SLAVE_NPU_DPM 98
#define SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG 99
#define SM8250_SLAVE_NPU_LLM_CFG 100
#define SM8250_SLAVE_NPU_TCM 101
#define SM8250_SLAVE_OCIMEM 102
#define SM8250_SLAVE_PCIE_0 103
#define SM8250_SLAVE_PCIE_0_CFG 104
#define SM8250_SLAVE_PCIE_1 105
#define SM8250_SLAVE_PCIE_1_CFG 106
#define SM8250_SLAVE_PCIE_2 107
#define SM8250_SLAVE_PCIE_2_CFG 108
#define SM8250_SLAVE_PDM 109
#define SM8250_SLAVE_PIMEM 110
#define SM8250_SLAVE_PIMEM_CFG 111
#define SM8250_SLAVE_PRNG 112
#define SM8250_SLAVE_QDSS_CFG 113
#define SM8250_SLAVE_QDSS_STM 114
#define SM8250_SLAVE_QSPI_0 115
#define SM8250_SLAVE_QUP_0 116
#define SM8250_SLAVE_QUP_1 117
#define SM8250_SLAVE_QUP_2 118
#define SM8250_SLAVE_RBCPR_CX_CFG 119
#define SM8250_SLAVE_RBCPR_MMCX_CFG 120
#define SM8250_SLAVE_RBCPR_MX_CFG 121
#define SM8250_SLAVE_SDCC_2 122
#define SM8250_SLAVE_SDCC_4 123
#define SM8250_SLAVE_SERVICE_A1NOC 124
#define SM8250_SLAVE_SERVICE_A2NOC 125
#define SM8250_SLAVE_SERVICE_CNOC 126
#define SM8250_SLAVE_SERVICE_GEM_NOC 127
#define SM8250_SLAVE_SERVICE_GEM_NOC_1 128
#define SM8250_SLAVE_SERVICE_GEM_NOC_2 129
#define SM8250_SLAVE_SERVICE_MNOC 130
#define SM8250_SLAVE_SERVICE_NPU_NOC 131
#define SM8250_SLAVE_SERVICE_SNOC 132
#define SM8250_SLAVE_SNOC_CFG 133
#define SM8250_SLAVE_SNOC_GEM_NOC_GC 134
#define SM8250_SLAVE_SNOC_GEM_NOC_SF 135
#define SM8250_SLAVE_TCSR 136
#define SM8250_SLAVE_TCU 137
#define SM8250_SLAVE_TLMM_NORTH 138
#define SM8250_SLAVE_TLMM_SOUTH 139
#define SM8250_SLAVE_TLMM_WEST 140
#define SM8250_SLAVE_TSIF 141
#define SM8250_SLAVE_UFS_CARD_CFG 142
#define SM8250_SLAVE_UFS_MEM_CFG 143
#define SM8250_SLAVE_USB3 144
#define SM8250_SLAVE_USB3_1 145
#define SM8250_SLAVE_VENUS_CFG 146
#define SM8250_SLAVE_VSENSE_CTRL_CFG 147
#define SM8250_SNOC_CNOC_MAS 148
#define SM8250_SNOC_CNOC_SLV 149
#define SM8250_MASTER_QUP_CORE_0 150
#define SM8250_MASTER_QUP_CORE_1 151
#define SM8250_MASTER_QUP_CORE_2 152
#define SM8250_SLAVE_QUP_CORE_0 153
#define SM8250_SLAVE_QUP_CORE_1 154
#define SM8250_SLAVE_QUP_CORE_2 155
#endif

684
drivers/interconnect/qcom/sm8350.c
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drivers/interconnect/qcom/sm8350.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm SM8350 interconnect IDs
*
* Copyright (c) 2021, Linaro Limited
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8350_H
#define __DRIVERS_INTERCONNECT_QCOM_SM8350_H
#define SM8350_MASTER_GPU_TCU 0
#define SM8350_MASTER_SYS_TCU 1
#define SM8350_MASTER_APPSS_PROC 2
#define SM8350_MASTER_LLCC 3
#define SM8350_MASTER_CNOC_LPASS_AG_NOC 4
#define SM8350_MASTER_CDSP_NOC_CFG 5
#define SM8350_MASTER_QDSS_BAM 6
#define SM8350_MASTER_QSPI_0 7
#define SM8350_MASTER_QUP_0 8
#define SM8350_MASTER_QUP_1 9
#define SM8350_MASTER_QUP_2 10
#define SM8350_MASTER_A1NOC_CFG 11
#define SM8350_MASTER_A2NOC_CFG 12
#define SM8350_MASTER_A1NOC_SNOC 13
#define SM8350_MASTER_A2NOC_SNOC 14
#define SM8350_MASTER_CAMNOC_HF 15
#define SM8350_MASTER_CAMNOC_ICP 16
#define SM8350_MASTER_CAMNOC_SF 17
#define SM8350_MASTER_COMPUTE_NOC 18
#define SM8350_MASTER_CNOC_DC_NOC 19
#define SM8350_MASTER_GEM_NOC_CFG 20
#define SM8350_MASTER_GEM_NOC_CNOC 21
#define SM8350_MASTER_GEM_NOC_PCIE_SNOC 22
#define SM8350_MASTER_GFX3D 23
#define SM8350_MASTER_CNOC_MNOC_CFG 24
#define SM8350_MASTER_MNOC_HF_MEM_NOC 25
#define SM8350_MASTER_MNOC_SF_MEM_NOC 26
#define SM8350_MASTER_ANOC_PCIE_GEM_NOC 27
#define SM8350_MASTER_SNOC_CFG 28
#define SM8350_MASTER_SNOC_GC_MEM_NOC 29
#define SM8350_MASTER_SNOC_SF_MEM_NOC 30
#define SM8350_MASTER_VIDEO_P0 31
#define SM8350_MASTER_VIDEO_P1 32
#define SM8350_MASTER_VIDEO_PROC 33
#define SM8350_MASTER_QUP_CORE_0 34
#define SM8350_MASTER_QUP_CORE_1 35
#define SM8350_MASTER_QUP_CORE_2 36
#define SM8350_MASTER_CRYPTO 37
#define SM8350_MASTER_IPA 38
#define SM8350_MASTER_MDP0 39
#define SM8350_MASTER_MDP1 40
#define SM8350_MASTER_CDSP_PROC 41
#define SM8350_MASTER_PIMEM 42
#define SM8350_MASTER_ROTATOR 43
#define SM8350_MASTER_GIC 44
#define SM8350_MASTER_PCIE_0 45
#define SM8350_MASTER_PCIE_1 46
#define SM8350_MASTER_QDSS_DAP 47
#define SM8350_MASTER_QDSS_ETR 48
#define SM8350_MASTER_SDCC_2 49
#define SM8350_MASTER_SDCC_4 50
#define SM8350_MASTER_UFS_CARD 51
#define SM8350_MASTER_UFS_MEM 52
#define SM8350_MASTER_USB3_0 53
#define SM8350_MASTER_USB3_1 54
#define SM8350_SLAVE_EBI1 55
#define SM8350_SLAVE_AHB2PHY_SOUTH 56
#define SM8350_SLAVE_AHB2PHY_NORTH 57
#define SM8350_SLAVE_AOSS 58
#define SM8350_SLAVE_APPSS 59
#define SM8350_SLAVE_CAMERA_CFG 60
#define SM8350_SLAVE_CLK_CTL 61
#define SM8350_SLAVE_CDSP_CFG 62
#define SM8350_SLAVE_RBCPR_CX_CFG 63
#define SM8350_SLAVE_RBCPR_MMCX_CFG 64
#define SM8350_SLAVE_RBCPR_MX_CFG 65
#define SM8350_SLAVE_CRYPTO_0_CFG 66
#define SM8350_SLAVE_CX_RDPM 67
#define SM8350_SLAVE_DCC_CFG 68
#define SM8350_SLAVE_DISPLAY_CFG 69
#define SM8350_SLAVE_GFX3D_CFG 70
#define SM8350_SLAVE_HWKM 71
#define SM8350_SLAVE_IMEM_CFG 72
#define SM8350_SLAVE_IPA_CFG 73
#define SM8350_SLAVE_IPC_ROUTER_CFG 74
#define SM8350_SLAVE_LLCC_CFG 75
#define SM8350_SLAVE_LPASS 76
#define SM8350_SLAVE_LPASS_CORE_CFG 77
#define SM8350_SLAVE_LPASS_LPI_CFG 78
#define SM8350_SLAVE_LPASS_MPU_CFG 79
#define SM8350_SLAVE_LPASS_TOP_CFG 80
#define SM8350_SLAVE_MSS_PROC_MS_MPU_CFG 81
#define SM8350_SLAVE_MCDMA_MS_MPU_CFG 82
#define SM8350_SLAVE_CNOC_MSS 83
#define SM8350_SLAVE_MX_RDPM 84
#define SM8350_SLAVE_PCIE_0_CFG 85
#define SM8350_SLAVE_PCIE_1_CFG 86
#define SM8350_SLAVE_PDM 87
#define SM8350_SLAVE_PIMEM_CFG 88
#define SM8350_SLAVE_PKA_WRAPPER_CFG 89
#define SM8350_SLAVE_PMU_WRAPPER_CFG 90
#define SM8350_SLAVE_QDSS_CFG 91
#define SM8350_SLAVE_QSPI_0 92
#define SM8350_SLAVE_QUP_0 93
#define SM8350_SLAVE_QUP_1 94
#define SM8350_SLAVE_QUP_2 95
#define SM8350_SLAVE_SDCC_2 96
#define SM8350_SLAVE_SDCC_4 97
#define SM8350_SLAVE_SECURITY 98
#define SM8350_SLAVE_SPSS_CFG 99
#define SM8350_SLAVE_TCSR 100
#define SM8350_SLAVE_TLMM 101
#define SM8350_SLAVE_UFS_CARD_CFG 102
#define SM8350_SLAVE_UFS_MEM_CFG 103
#define SM8350_SLAVE_USB3_0 104
#define SM8350_SLAVE_USB3_1 105
#define SM8350_SLAVE_VENUS_CFG 106
#define SM8350_SLAVE_VSENSE_CTRL_CFG 107
#define SM8350_SLAVE_A1NOC_CFG 108
#define SM8350_SLAVE_A1NOC_SNOC 109
#define SM8350_SLAVE_A2NOC_CFG 110
#define SM8350_SLAVE_A2NOC_SNOC 111
#define SM8350_SLAVE_DDRSS_CFG 112
#define SM8350_SLAVE_GEM_NOC_CNOC 113
#define SM8350_SLAVE_GEM_NOC_CFG 114
#define SM8350_SLAVE_SNOC_GEM_NOC_GC 115
#define SM8350_SLAVE_SNOC_GEM_NOC_SF 116
#define SM8350_SLAVE_LLCC 117
#define SM8350_SLAVE_MNOC_HF_MEM_NOC 118
#define SM8350_SLAVE_MNOC_SF_MEM_NOC 119
#define SM8350_SLAVE_CNOC_MNOC_CFG 120
#define SM8350_SLAVE_CDSP_MEM_NOC 121
#define SM8350_SLAVE_MEM_NOC_PCIE_SNOC 122
#define SM8350_SLAVE_ANOC_PCIE_GEM_NOC 123
#define SM8350_SLAVE_SNOC_CFG 124
#define SM8350_SLAVE_QUP_CORE_0 125
#define SM8350_SLAVE_QUP_CORE_1 126
#define SM8350_SLAVE_QUP_CORE_2 127
#define SM8350_SLAVE_BOOT_IMEM 128
#define SM8350_SLAVE_IMEM 129
#define SM8350_SLAVE_PIMEM 130
#define SM8350_SLAVE_SERVICE_NSP_NOC 131
#define SM8350_SLAVE_SERVICE_A1NOC 132
#define SM8350_SLAVE_SERVICE_A2NOC 133
#define SM8350_SLAVE_SERVICE_CNOC 134
#define SM8350_SLAVE_SERVICE_GEM_NOC_1 135
#define SM8350_SLAVE_SERVICE_MNOC 136
#define SM8350_SLAVE_SERVICES_LPASS_AML_NOC 137
#define SM8350_SLAVE_SERVICE_LPASS_AG_NOC 138
#define SM8350_SLAVE_SERVICE_GEM_NOC_2 139
#define SM8350_SLAVE_SERVICE_SNOC 140
#define SM8350_SLAVE_SERVICE_GEM_NOC 141
#define SM8350_SLAVE_PCIE_0 142
#define SM8350_SLAVE_PCIE_1 143
#define SM8350_SLAVE_QDSS_STM 144
#define SM8350_SLAVE_TCU 145
#endif

601
drivers/interconnect/qcom/sm8450.c
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drivers/interconnect/qcom/sm8450.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* SM8450 interconnect IDs
*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Linaro Limited
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H
#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H
#define SM8450_MASTER_GPU_TCU 0
#define SM8450_MASTER_SYS_TCU 1
#define SM8450_MASTER_APPSS_PROC 2
#define SM8450_MASTER_LLCC 3
#define SM8450_MASTER_CNOC_LPASS_AG_NOC 4
#define SM8450_MASTER_GIC_AHB 5
#define SM8450_MASTER_CDSP_NOC_CFG 6
#define SM8450_MASTER_QDSS_BAM 7
#define SM8450_MASTER_QSPI_0 8
#define SM8450_MASTER_QUP_0 9
#define SM8450_MASTER_QUP_1 10
#define SM8450_MASTER_QUP_2 11
#define SM8450_MASTER_A1NOC_CFG 12
#define SM8450_MASTER_A2NOC_CFG 13
#define SM8450_MASTER_A1NOC_SNOC 14
#define SM8450_MASTER_A2NOC_SNOC 15
#define SM8450_MASTER_CAMNOC_HF 16
#define SM8450_MASTER_CAMNOC_ICP 17
#define SM8450_MASTER_CAMNOC_SF 18
#define SM8450_MASTER_GEM_NOC_CNOC 19
#define SM8450_MASTER_GEM_NOC_PCIE_SNOC 20
#define SM8450_MASTER_GFX3D 21
#define SM8450_MASTER_LPASS_ANOC 22
#define SM8450_MASTER_MDP 23
#define SM8450_MASTER_MDP0 SM8450_MASTER_MDP
#define SM8450_MASTER_MDP1 SM8450_MASTER_MDP
#define SM8450_MASTER_MSS_PROC 24
#define SM8450_MASTER_CNOC_MNOC_CFG 25
#define SM8450_MASTER_MNOC_HF_MEM_NOC 26
#define SM8450_MASTER_MNOC_SF_MEM_NOC 27
#define SM8450_MASTER_COMPUTE_NOC 28
#define SM8450_MASTER_ANOC_PCIE_GEM_NOC 29
#define SM8450_MASTER_PCIE_ANOC_CFG 30
#define SM8450_MASTER_ROTATOR 31
#define SM8450_MASTER_SNOC_CFG 32
#define SM8450_MASTER_SNOC_GC_MEM_NOC 33
#define SM8450_MASTER_SNOC_SF_MEM_NOC 34
#define SM8450_MASTER_CDSP_HCP 35
#define SM8450_MASTER_VIDEO 36
#define SM8450_MASTER_VIDEO_P0 SM8450_MASTER_VIDEO
#define SM8450_MASTER_VIDEO_P1 SM8450_MASTER_VIDEO
#define SM8450_MASTER_VIDEO_CV_PROC 37
#define SM8450_MASTER_VIDEO_PROC 38
#define SM8450_MASTER_VIDEO_V_PROC 39
#define SM8450_MASTER_QUP_CORE_0 40
#define SM8450_MASTER_QUP_CORE_1 41
#define SM8450_MASTER_QUP_CORE_2 42
#define SM8450_MASTER_CRYPTO 43
#define SM8450_MASTER_IPA 44
#define SM8450_MASTER_LPASS_PROC 45
#define SM8450_MASTER_CDSP_PROC 46
#define SM8450_MASTER_PIMEM 47
#define SM8450_MASTER_SENSORS_PROC 48
#define SM8450_MASTER_SP 49
#define SM8450_MASTER_GIC 50
#define SM8450_MASTER_PCIE_0 51
#define SM8450_MASTER_PCIE_1 52
#define SM8450_MASTER_QDSS_ETR 53
#define SM8450_MASTER_QDSS_ETR_1 54
#define SM8450_MASTER_SDCC_2 55
#define SM8450_MASTER_SDCC_4 56
#define SM8450_MASTER_UFS_MEM 57
#define SM8450_MASTER_USB3_0 58
#define SM8450_SLAVE_EBI1 512
#define SM8450_SLAVE_AHB2PHY_SOUTH 513
#define SM8450_SLAVE_AHB2PHY_NORTH 514
#define SM8450_SLAVE_AOSS 515
#define SM8450_SLAVE_CAMERA_CFG 516
#define SM8450_SLAVE_CLK_CTL 517
#define SM8450_SLAVE_CDSP_CFG 518
#define SM8450_SLAVE_RBCPR_CX_CFG 519
#define SM8450_SLAVE_RBCPR_MMCX_CFG 520
#define SM8450_SLAVE_RBCPR_MXA_CFG 521
#define SM8450_SLAVE_RBCPR_MXC_CFG 522
#define SM8450_SLAVE_CRYPTO_0_CFG 523
#define SM8450_SLAVE_CX_RDPM 524
#define SM8450_SLAVE_DISPLAY_CFG 525
#define SM8450_SLAVE_GFX3D_CFG 526
#define SM8450_SLAVE_IMEM_CFG 527
#define SM8450_SLAVE_IPA_CFG 528
#define SM8450_SLAVE_IPC_ROUTER_CFG 529
#define SM8450_SLAVE_LPASS 530
#define SM8450_SLAVE_LPASS_CORE_CFG 531
#define SM8450_SLAVE_LPASS_LPI_CFG 532
#define SM8450_SLAVE_LPASS_MPU_CFG 533
#define SM8450_SLAVE_LPASS_TOP_CFG 534
#define SM8450_SLAVE_CNOC_MSS 535
#define SM8450_SLAVE_MX_RDPM 536
#define SM8450_SLAVE_PCIE_0_CFG 537
#define SM8450_SLAVE_PCIE_1_CFG 538
#define SM8450_SLAVE_PDM 539
#define SM8450_SLAVE_PIMEM_CFG 540
#define SM8450_SLAVE_PRNG 541
#define SM8450_SLAVE_QDSS_CFG 542
#define SM8450_SLAVE_QSPI_0 543
#define SM8450_SLAVE_QUP_0 544
#define SM8450_SLAVE_QUP_1 545
#define SM8450_SLAVE_QUP_2 546
#define SM8450_SLAVE_SDCC_2 547
#define SM8450_SLAVE_SDCC_4 548
#define SM8450_SLAVE_SPSS_CFG 549
#define SM8450_SLAVE_TCSR 550
#define SM8450_SLAVE_TLMM 551
#define SM8450_SLAVE_TME_CFG 552
#define SM8450_SLAVE_UFS_MEM_CFG 553
#define SM8450_SLAVE_USB3_0 554
#define SM8450_SLAVE_VENUS_CFG 555
#define SM8450_SLAVE_VSENSE_CTRL_CFG 556
#define SM8450_SLAVE_A1NOC_CFG 557
#define SM8450_SLAVE_A1NOC_SNOC 558
#define SM8450_SLAVE_A2NOC_CFG 559
#define SM8450_SLAVE_A2NOC_SNOC 560
#define SM8450_SLAVE_DDRSS_CFG 561
#define SM8450_SLAVE_GEM_NOC_CNOC 562
#define SM8450_SLAVE_SNOC_GEM_NOC_GC 563
#define SM8450_SLAVE_SNOC_GEM_NOC_SF 564
#define SM8450_SLAVE_LLCC 565
#define SM8450_SLAVE_MNOC_HF_MEM_NOC 566
#define SM8450_SLAVE_MNOC_SF_MEM_NOC 567
#define SM8450_SLAVE_CNOC_MNOC_CFG 568
#define SM8450_SLAVE_CDSP_MEM_NOC 569
#define SM8450_SLAVE_MEM_NOC_PCIE_SNOC 570
#define SM8450_SLAVE_PCIE_ANOC_CFG 571
#define SM8450_SLAVE_ANOC_PCIE_GEM_NOC 572
#define SM8450_SLAVE_SNOC_CFG 573
#define SM8450_SLAVE_LPASS_SNOC 574
#define SM8450_SLAVE_QUP_CORE_0 575
#define SM8450_SLAVE_QUP_CORE_1 576
#define SM8450_SLAVE_QUP_CORE_2 577
#define SM8450_SLAVE_IMEM 578
#define SM8450_SLAVE_PIMEM 579
#define SM8450_SLAVE_SERVICE_NSP_NOC 580
#define SM8450_SLAVE_SERVICE_A1NOC 581
#define SM8450_SLAVE_SERVICE_A2NOC 582
#define SM8450_SLAVE_SERVICE_CNOC 583
#define SM8450_SLAVE_SERVICE_MNOC 584
#define SM8450_SLAVE_SERVICES_LPASS_AML_NOC 585
#define SM8450_SLAVE_SERVICE_LPASS_AG_NOC 586
#define SM8450_SLAVE_SERVICE_PCIE_ANOC 587
#define SM8450_SLAVE_SERVICE_SNOC 588
#define SM8450_SLAVE_PCIE_0 589
#define SM8450_SLAVE_PCIE_1 590
#define SM8450_SLAVE_QDSS_STM 591
#define SM8450_SLAVE_TCU 592
#define SM8450_MASTER_LLCC_DISP 1000
#define SM8450_MASTER_MDP_DISP 1001
#define SM8450_MASTER_MDP0_DISP SM8450_MASTER_MDP_DISP
#define SM8450_MASTER_MDP1_DISP SM8450_MASTER_MDP_DISP
#define SM8450_MASTER_MNOC_HF_MEM_NOC_DISP 1002
#define SM8450_MASTER_MNOC_SF_MEM_NOC_DISP 1003
#define SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP 1004
#define SM8450_MASTER_ROTATOR_DISP 1005
#define SM8450_SLAVE_EBI1_DISP 1512
#define SM8450_SLAVE_LLCC_DISP 1513
#define SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP 1514
#define SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP 1515
#endif

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drivers/interconnect/qcom/sm8550.c
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drivers/interconnect/qcom/sm8550.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* SM8450 interconnect IDs
*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Linaro Limited
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H
#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H
#define SM8550_MASTER_A1NOC_SNOC 0
#define SM8550_MASTER_A2NOC_SNOC 1
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC 2
#define SM8550_MASTER_APPSS_PROC 3
#define SM8550_MASTER_CAMNOC_HF 4
#define SM8550_MASTER_CAMNOC_ICP 5
#define SM8550_MASTER_CAMNOC_SF 6
#define SM8550_MASTER_CDSP_HCP 7
#define SM8550_MASTER_CDSP_PROC 8
#define SM8550_MASTER_CNOC_CFG 9
#define SM8550_MASTER_CNOC_MNOC_CFG 10
#define SM8550_MASTER_COMPUTE_NOC 11
#define SM8550_MASTER_CRYPTO 12
#define SM8550_MASTER_GEM_NOC_CNOC 13
#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 14
#define SM8550_MASTER_GFX3D 15
#define SM8550_MASTER_GIC 16
#define SM8550_MASTER_GIC_AHB 17
#define SM8550_MASTER_GPU_TCU 18
#define SM8550_MASTER_IPA 19
#define SM8550_MASTER_LLCC 20
#define SM8550_MASTER_LPASS_GEM_NOC 21
#define SM8550_MASTER_LPASS_LPINOC 22
#define SM8550_MASTER_LPASS_PROC 23
#define SM8550_MASTER_LPIAON_NOC 24
#define SM8550_MASTER_MDP 25
#define SM8550_MASTER_MNOC_HF_MEM_NOC 26
#define SM8550_MASTER_MNOC_SF_MEM_NOC 27
#define SM8550_MASTER_MSS_PROC 28
#define SM8550_MASTER_PCIE_0 29
#define SM8550_MASTER_PCIE_1 30
#define SM8550_MASTER_PCIE_ANOC_CFG 31
#define SM8550_MASTER_QDSS_BAM 32
#define SM8550_MASTER_QDSS_ETR 33
#define SM8550_MASTER_QDSS_ETR_1 34
#define SM8550_MASTER_QSPI_0 35
#define SM8550_MASTER_QUP_1 36
#define SM8550_MASTER_QUP_2 37
#define SM8550_MASTER_QUP_CORE_0 38
#define SM8550_MASTER_QUP_CORE_1 39
#define SM8550_MASTER_QUP_CORE_2 40
#define SM8550_MASTER_SDCC_2 41
#define SM8550_MASTER_SDCC_4 42
#define SM8550_MASTER_SNOC_GC_MEM_NOC 43
#define SM8550_MASTER_SNOC_SF_MEM_NOC 44
#define SM8550_MASTER_SP 45
#define SM8550_MASTER_SYS_TCU 46
#define SM8550_MASTER_UFS_MEM 47
#define SM8550_MASTER_USB3_0 48
#define SM8550_MASTER_VIDEO 49
#define SM8550_MASTER_VIDEO_CV_PROC 50
#define SM8550_MASTER_VIDEO_PROC 51
#define SM8550_MASTER_VIDEO_V_PROC 52
#define SM8550_SLAVE_A1NOC_SNOC 53
#define SM8550_SLAVE_A2NOC_SNOC 54
#define SM8550_SLAVE_AHB2PHY_NORTH 55
#define SM8550_SLAVE_AHB2PHY_SOUTH 56
#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 57
#define SM8550_SLAVE_AOSS 58
#define SM8550_SLAVE_APPSS 59
#define SM8550_SLAVE_BOOT_IMEM 60
#define SM8550_SLAVE_CAMERA_CFG 61
#define SM8550_SLAVE_CDSP_MEM_NOC 62
#define SM8550_SLAVE_CLK_CTL 63
#define SM8550_SLAVE_CNOC_CFG 64
#define SM8550_SLAVE_CNOC_MNOC_CFG 65
#define SM8550_SLAVE_CNOC_MSS 66
#define SM8550_SLAVE_CPR_NSPCX 67
#define SM8550_SLAVE_CRYPTO_0_CFG 68
#define SM8550_SLAVE_CX_RDPM 69
#define SM8550_SLAVE_DDRSS_CFG 70
#define SM8550_SLAVE_DISPLAY_CFG 71
#define SM8550_SLAVE_EBI1 72
#define SM8550_SLAVE_GEM_NOC_CNOC 73
#define SM8550_SLAVE_GFX3D_CFG 74
#define SM8550_SLAVE_I2C 75
#define SM8550_SLAVE_IMEM 76
#define SM8550_SLAVE_IMEM_CFG 77
#define SM8550_SLAVE_IPA_CFG 78
#define SM8550_SLAVE_IPC_ROUTER_CFG 79
#define SM8550_SLAVE_LLCC 80
#define SM8550_SLAVE_LPASS_GEM_NOC 81
#define SM8550_SLAVE_LPASS_QTB_CFG 82
#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 83
#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 84
#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 85
#define SM8550_SLAVE_MNOC_HF_MEM_NOC 86
#define SM8550_SLAVE_MNOC_SF_MEM_NOC 87
#define SM8550_SLAVE_MX_RDPM 88
#define SM8550_SLAVE_NSP_QTB_CFG 89
#define SM8550_SLAVE_PCIE_0 90
#define SM8550_SLAVE_PCIE_0_CFG 91
#define SM8550_SLAVE_PCIE_1 92
#define SM8550_SLAVE_PCIE_1_CFG 93
#define SM8550_SLAVE_PCIE_ANOC_CFG 94
#define SM8550_SLAVE_PDM 95
#define SM8550_SLAVE_PIMEM_CFG 96
#define SM8550_SLAVE_PRNG 97
#define SM8550_SLAVE_QDSS_CFG 98
#define SM8550_SLAVE_QDSS_STM 99
#define SM8550_SLAVE_QSPI_0 100
#define SM8550_SLAVE_QUP_1 101
#define SM8550_SLAVE_QUP_2 102
#define SM8550_SLAVE_QUP_CORE_0 103
#define SM8550_SLAVE_QUP_CORE_1 104
#define SM8550_SLAVE_QUP_CORE_2 105
#define SM8550_SLAVE_RBCPR_CX_CFG 106
#define SM8550_SLAVE_RBCPR_MMCX_CFG 107
#define SM8550_SLAVE_RBCPR_MXA_CFG 108
#define SM8550_SLAVE_RBCPR_MXC_CFG 109
#define SM8550_SLAVE_SDCC_2 110
#define SM8550_SLAVE_SDCC_4 111
#define SM8550_SLAVE_SERVICE_MNOC 112
#define SM8550_SLAVE_SERVICE_PCIE_ANOC 113
#define SM8550_SLAVE_SNOC_GEM_NOC_GC 114
#define SM8550_SLAVE_SNOC_GEM_NOC_SF 115
#define SM8550_SLAVE_SPSS_CFG 116
#define SM8550_SLAVE_TCSR 117
#define SM8550_SLAVE_TCU 118
#define SM8550_SLAVE_TLMM 119
#define SM8550_SLAVE_TME_CFG 120
#define SM8550_SLAVE_UFS_MEM_CFG 121
#define SM8550_SLAVE_USB3_0 122
#define SM8550_SLAVE_VENUS_CFG 123
#define SM8550_SLAVE_VSENSE_CTRL_CFG 124
#endif

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drivers/interconnect/qcom/sm8650.c
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drivers/interconnect/qcom/sm8650.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* SM8650 interconnect IDs
*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8650_H
#define __DRIVERS_INTERCONNECT_QCOM_SM8650_H
#define SM8650_MASTER_A1NOC_SNOC 0
#define SM8650_MASTER_A2NOC_SNOC 1
#define SM8650_MASTER_ANOC_PCIE_GEM_NOC 2
#define SM8650_MASTER_APPSS_PROC 3
#define SM8650_MASTER_CAMNOC_HF 4
#define SM8650_MASTER_CAMNOC_ICP 5
#define SM8650_MASTER_CAMNOC_SF 6
#define SM8650_MASTER_CDSP_HCP 7
#define SM8650_MASTER_CDSP_PROC 8
#define SM8650_MASTER_CNOC_CFG 9
#define SM8650_MASTER_CNOC_MNOC_CFG 10
#define SM8650_MASTER_COMPUTE_NOC 11
#define SM8650_MASTER_CRYPTO 12
#define SM8650_MASTER_GEM_NOC_CNOC 13
#define SM8650_MASTER_GEM_NOC_PCIE_SNOC 14
#define SM8650_MASTER_GFX3D 15
#define SM8650_MASTER_GIC 16
#define SM8650_MASTER_GPU_TCU 17
#define SM8650_MASTER_IPA 18
#define SM8650_MASTER_LLCC 19
#define SM8650_MASTER_LPASS_GEM_NOC 20
#define SM8650_MASTER_LPASS_LPINOC 21
#define SM8650_MASTER_LPASS_PROC 22
#define SM8650_MASTER_LPIAON_NOC 23
#define SM8650_MASTER_MDP 24
#define SM8650_MASTER_MNOC_HF_MEM_NOC 25
#define SM8650_MASTER_MNOC_SF_MEM_NOC 26
#define SM8650_MASTER_MSS_PROC 27
#define SM8650_MASTER_PCIE_0 28
#define SM8650_MASTER_PCIE_1 29
#define SM8650_MASTER_PCIE_ANOC_CFG 30
#define SM8650_MASTER_QDSS_BAM 31
#define SM8650_MASTER_QDSS_ETR 32
#define SM8650_MASTER_QDSS_ETR_1 33
#define SM8650_MASTER_QSPI_0 34
#define SM8650_MASTER_QUP_1 35
#define SM8650_MASTER_QUP_2 36
#define SM8650_MASTER_QUP_3 37
#define SM8650_MASTER_QUP_CORE_0 38
#define SM8650_MASTER_QUP_CORE_1 39
#define SM8650_MASTER_QUP_CORE_2 40
#define SM8650_MASTER_SDCC_2 41
#define SM8650_MASTER_SDCC_4 42
#define SM8650_MASTER_SNOC_SF_MEM_NOC 43
#define SM8650_MASTER_SP 44
#define SM8650_MASTER_SYS_TCU 45
#define SM8650_MASTER_UBWC_P 46
#define SM8650_MASTER_UBWC_P_TCU 47
#define SM8650_MASTER_UFS_MEM 48
#define SM8650_MASTER_USB3_0 49
#define SM8650_MASTER_VIDEO 50
#define SM8650_MASTER_VIDEO_CV_PROC 51
#define SM8650_MASTER_VIDEO_PROC 52
#define SM8650_MASTER_VIDEO_V_PROC 53
#define SM8650_SLAVE_A1NOC_SNOC 54
#define SM8650_SLAVE_A2NOC_SNOC 55
#define SM8650_SLAVE_AHB2PHY_NORTH 56
#define SM8650_SLAVE_AHB2PHY_SOUTH 57
#define SM8650_SLAVE_ANOC_PCIE_GEM_NOC 58
#define SM8650_SLAVE_AOSS 59
#define SM8650_SLAVE_APPSS 60
#define SM8650_SLAVE_CAMERA_CFG 61
#define SM8650_SLAVE_CDSP_MEM_NOC 62
#define SM8650_SLAVE_CLK_CTL 63
#define SM8650_SLAVE_CNOC_CFG 64
#define SM8650_SLAVE_CNOC_MNOC_CFG 65
#define SM8650_SLAVE_CNOC_MSS 66
#define SM8650_SLAVE_CPR_HMX 67
#define SM8650_SLAVE_CPR_NSPCX 68
#define SM8650_SLAVE_CRYPTO_0_CFG 69
#define SM8650_SLAVE_CX_RDPM 70
#define SM8650_SLAVE_DDRSS_CFG 71
#define SM8650_SLAVE_DISPLAY_CFG 72
#define SM8650_SLAVE_EBI1 73
#define SM8650_SLAVE_GEM_NOC_CNOC 74
#define SM8650_SLAVE_GFX3D_CFG 75
#define SM8650_SLAVE_I2C 76
#define SM8650_SLAVE_I3C_IBI0_CFG 77
#define SM8650_SLAVE_I3C_IBI1_CFG 78
#define SM8650_SLAVE_IMEM 79
#define SM8650_SLAVE_IMEM_CFG 80
#define SM8650_SLAVE_IPA_CFG 81
#define SM8650_SLAVE_IPC_ROUTER_CFG 82
#define SM8650_SLAVE_LLCC 83
#define SM8650_SLAVE_LPASS_GEM_NOC 84
#define SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC 85
#define SM8650_SLAVE_LPICX_NOC_LPIAON_NOC 86
#define SM8650_SLAVE_MEM_NOC_PCIE_SNOC 87
#define SM8650_SLAVE_MNOC_HF_MEM_NOC 88
#define SM8650_SLAVE_MNOC_SF_MEM_NOC 89
#define SM8650_SLAVE_MX_2_RDPM 90
#define SM8650_SLAVE_MX_RDPM 91
#define SM8650_SLAVE_NSP_QTB_CFG 92
#define SM8650_SLAVE_PCIE_0 93
#define SM8650_SLAVE_PCIE_1 94
#define SM8650_SLAVE_PCIE_0_CFG 95
#define SM8650_SLAVE_PCIE_1_CFG 96
#define SM8650_SLAVE_PCIE_ANOC_CFG 97
#define SM8650_SLAVE_PCIE_RSCC 98
#define SM8650_SLAVE_PDM 99
#define SM8650_SLAVE_PRNG 100
#define SM8650_SLAVE_QDSS_CFG 101
#define SM8650_SLAVE_QDSS_STM 102
#define SM8650_SLAVE_QSPI_0 103
#define SM8650_SLAVE_QUP_1 104
#define SM8650_SLAVE_QUP_2 105
#define SM8650_SLAVE_QUP_3 106
#define SM8650_SLAVE_QUP_CORE_0 107
#define SM8650_SLAVE_QUP_CORE_1 108
#define SM8650_SLAVE_QUP_CORE_2 109
#define SM8650_SLAVE_RBCPR_CX_CFG 110
#define SM8650_SLAVE_RBCPR_MMCX_CFG 111
#define SM8650_SLAVE_RBCPR_MXA_CFG 112
#define SM8650_SLAVE_RBCPR_MXC_CFG 113
#define SM8650_SLAVE_SDCC_2 114
#define SM8650_SLAVE_SDCC_4 115
#define SM8650_SLAVE_SERVICE_CNOC 116
#define SM8650_SLAVE_SERVICE_CNOC_CFG 117
#define SM8650_SLAVE_SERVICE_MNOC 118
#define SM8650_SLAVE_SERVICE_PCIE_ANOC 119
#define SM8650_SLAVE_SNOC_GEM_NOC_SF 120
#define SM8650_SLAVE_SPSS_CFG 121
#define SM8650_SLAVE_TCSR 122
#define SM8650_SLAVE_TCU 123
#define SM8650_SLAVE_TLMM 124
#define SM8650_SLAVE_TME_CFG 125
#define SM8650_SLAVE_UFS_MEM_CFG 126
#define SM8650_SLAVE_USB3_0 127
#define SM8650_SLAVE_VENUS_CFG 128
#define SM8650_SLAVE_VSENSE_CTRL_CFG 129
#define SM8650_MASTER_APSS_NOC 130
#endif

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drivers/interconnect/qcom/sm8750.c
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drivers/interconnect/qcom/x1e80100.c
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drivers/interconnect/qcom/x1e80100.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* X1E80100 interconnect IDs
*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_X1E80100_H
#define __DRIVERS_INTERCONNECT_QCOM_X1E80100_H
#define X1E80100_MASTER_A1NOC_SNOC 0
#define X1E80100_MASTER_A2NOC_SNOC 1
#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC 2
#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP 3
#define X1E80100_MASTER_APPSS_PROC 4
#define X1E80100_MASTER_CAMNOC_HF 5
#define X1E80100_MASTER_CAMNOC_ICP 6
#define X1E80100_MASTER_CAMNOC_SF 7
#define X1E80100_MASTER_CDSP_PROC 8
#define X1E80100_MASTER_CNOC_CFG 9
#define X1E80100_MASTER_CNOC_MNOC_CFG 10
#define X1E80100_MASTER_COMPUTE_NOC 11
#define X1E80100_MASTER_CRYPTO 12
#define X1E80100_MASTER_GEM_NOC_CNOC 13
#define X1E80100_MASTER_GEM_NOC_PCIE_SNOC 14
#define X1E80100_MASTER_GFX3D 15
#define X1E80100_MASTER_GPU_TCU 16
#define X1E80100_MASTER_IPA 17
#define X1E80100_MASTER_LLCC 18
#define X1E80100_MASTER_LLCC_DISP 19
#define X1E80100_MASTER_LPASS_GEM_NOC 20
#define X1E80100_MASTER_LPASS_LPINOC 21
#define X1E80100_MASTER_LPASS_PROC 22
#define X1E80100_MASTER_LPIAON_NOC 23
#define X1E80100_MASTER_MDP 24
#define X1E80100_MASTER_MDP_DISP 25
#define X1E80100_MASTER_MNOC_HF_MEM_NOC 26
#define X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP 27
#define X1E80100_MASTER_MNOC_SF_MEM_NOC 28
#define X1E80100_MASTER_PCIE_0 29
#define X1E80100_MASTER_PCIE_1 30
#define X1E80100_MASTER_QDSS_ETR 31
#define X1E80100_MASTER_QDSS_ETR_1 32
#define X1E80100_MASTER_QSPI_0 33
#define X1E80100_MASTER_QUP_0 34
#define X1E80100_MASTER_QUP_1 35
#define X1E80100_MASTER_QUP_2 36
#define X1E80100_MASTER_QUP_CORE_0 37
#define X1E80100_MASTER_QUP_CORE_1 38
#define X1E80100_MASTER_SDCC_2 39
#define X1E80100_MASTER_SDCC_4 40
#define X1E80100_MASTER_SNOC_SF_MEM_NOC 41
#define X1E80100_MASTER_SP 42
#define X1E80100_MASTER_SYS_TCU 43
#define X1E80100_MASTER_UFS_MEM 44
#define X1E80100_MASTER_USB3_0 45
#define X1E80100_MASTER_VIDEO 46
#define X1E80100_MASTER_VIDEO_CV_PROC 47
#define X1E80100_MASTER_VIDEO_V_PROC 48
#define X1E80100_SLAVE_A1NOC_SNOC 49
#define X1E80100_SLAVE_A2NOC_SNOC 50
#define X1E80100_SLAVE_AHB2PHY_NORTH 51
#define X1E80100_SLAVE_AHB2PHY_SOUTH 52
#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC 53
#define X1E80100_SLAVE_AOSS 54
#define X1E80100_SLAVE_APPSS 55
#define X1E80100_SLAVE_BOOT_IMEM 56
#define X1E80100_SLAVE_CAMERA_CFG 57
#define X1E80100_SLAVE_CDSP_MEM_NOC 58
#define X1E80100_SLAVE_CLK_CTL 59
#define X1E80100_SLAVE_CNOC_CFG 60
#define X1E80100_SLAVE_CNOC_MNOC_CFG 61
#define X1E80100_SLAVE_CRYPTO_0_CFG 62
#define X1E80100_SLAVE_DISPLAY_CFG 63
#define X1E80100_SLAVE_EBI1 64
#define X1E80100_SLAVE_EBI1_DISP 65
#define X1E80100_SLAVE_GEM_NOC_CNOC 66
#define X1E80100_SLAVE_GFX3D_CFG 67
#define X1E80100_SLAVE_IMEM 68
#define X1E80100_SLAVE_IMEM_CFG 69
#define X1E80100_SLAVE_IPC_ROUTER_CFG 70
#define X1E80100_SLAVE_LLCC 71
#define X1E80100_SLAVE_LLCC_DISP 72
#define X1E80100_SLAVE_LPASS_GEM_NOC 73
#define X1E80100_SLAVE_LPASS_QTB_CFG 74
#define X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC 75
#define X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC 76
#define X1E80100_SLAVE_MEM_NOC_PCIE_SNOC 77
#define X1E80100_SLAVE_MNOC_HF_MEM_NOC 78
#define X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP 79
#define X1E80100_SLAVE_MNOC_SF_MEM_NOC 80
#define X1E80100_SLAVE_NSP_QTB_CFG 81
#define X1E80100_SLAVE_PCIE_0 82
#define X1E80100_SLAVE_PCIE_0_CFG 83
#define X1E80100_SLAVE_PCIE_1 84
#define X1E80100_SLAVE_PCIE_1_CFG 85
#define X1E80100_SLAVE_PDM 86
#define X1E80100_SLAVE_PRNG 87
#define X1E80100_SLAVE_QDSS_CFG 88
#define X1E80100_SLAVE_QDSS_STM 89
#define X1E80100_SLAVE_QSPI_0 90
#define X1E80100_SLAVE_QUP_1 91
#define X1E80100_SLAVE_QUP_2 92
#define X1E80100_SLAVE_QUP_CORE_0 93
#define X1E80100_SLAVE_QUP_CORE_1 94
#define X1E80100_SLAVE_QUP_CORE_2 95
#define X1E80100_SLAVE_SDCC_2 96
#define X1E80100_SLAVE_SDCC_4 97
#define X1E80100_SLAVE_SERVICE_MNOC 98
#define X1E80100_SLAVE_SNOC_GEM_NOC_SF 99
#define X1E80100_SLAVE_TCSR 100
#define X1E80100_SLAVE_TCU 101
#define X1E80100_SLAVE_TLMM 102
#define X1E80100_SLAVE_TME_CFG 103
#define X1E80100_SLAVE_UFS_MEM_CFG 104
#define X1E80100_SLAVE_USB3_0 105
#define X1E80100_SLAVE_VENUS_CFG 106
#define X1E80100_MASTER_DDR_PERF_MODE 107
#define X1E80100_MASTER_QUP_CORE_2 108
#define X1E80100_MASTER_PCIE_TCU 109
#define X1E80100_MASTER_GIC2 110
#define X1E80100_MASTER_AV1_ENC 111
#define X1E80100_MASTER_EVA 112
#define X1E80100_MASTER_PCIE_NORTH 113
#define X1E80100_MASTER_PCIE_SOUTH 114
#define X1E80100_MASTER_PCIE_3 115
#define X1E80100_MASTER_PCIE_4 116
#define X1E80100_MASTER_PCIE_5 117
#define X1E80100_MASTER_PCIE_2 118
#define X1E80100_MASTER_PCIE_6A 119
#define X1E80100_MASTER_PCIE_6B 120
#define X1E80100_MASTER_GIC1 121
#define X1E80100_MASTER_USB_NOC_SNOC 122
#define X1E80100_MASTER_AGGRE_USB_NORTH 123
#define X1E80100_MASTER_AGGRE_USB_SOUTH 124
#define X1E80100_MASTER_USB2 125
#define X1E80100_MASTER_USB3_MP 126
#define X1E80100_MASTER_USB3_1 127
#define X1E80100_MASTER_USB3_2 128
#define X1E80100_MASTER_USB4_0 129
#define X1E80100_MASTER_USB4_1 130
#define X1E80100_MASTER_USB4_2 131
#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE 132
#define X1E80100_MASTER_LLCC_PCIE 133
#define X1E80100_MASTER_PCIE_NORTH_PCIE 134
#define X1E80100_MASTER_PCIE_SOUTH_PCIE 135
#define X1E80100_MASTER_PCIE_3_PCIE 136
#define X1E80100_MASTER_PCIE_4_PCIE 137
#define X1E80100_MASTER_PCIE_5_PCIE 138
#define X1E80100_MASTER_PCIE_0_PCIE 139
#define X1E80100_MASTER_PCIE_1_PCIE 140
#define X1E80100_MASTER_PCIE_2_PCIE 141
#define X1E80100_MASTER_PCIE_6A_PCIE 142
#define X1E80100_MASTER_PCIE_6B_PCIE 143
#define X1E80100_SLAVE_AHB2PHY_2 144
#define X1E80100_SLAVE_AV1_ENC_CFG 145
#define X1E80100_SLAVE_PCIE_2_CFG 146
#define X1E80100_SLAVE_PCIE_3_CFG 147
#define X1E80100_SLAVE_PCIE_4_CFG 148
#define X1E80100_SLAVE_PCIE_5_CFG 149
#define X1E80100_SLAVE_PCIE_6A_CFG 150
#define X1E80100_SLAVE_PCIE_6B_CFG 151
#define X1E80100_SLAVE_PCIE_RSC_CFG 152
#define X1E80100_SLAVE_QUP_0 153
#define X1E80100_SLAVE_SMMUV3_CFG 154
#define X1E80100_SLAVE_USB2 155
#define X1E80100_SLAVE_USB3_1 156
#define X1E80100_SLAVE_USB3_2 157
#define X1E80100_SLAVE_USB3_MP 158
#define X1E80100_SLAVE_USB4_0 159
#define X1E80100_SLAVE_USB4_1 160
#define X1E80100_SLAVE_USB4_2 161
#define X1E80100_SLAVE_PCIE_2 162
#define X1E80100_SLAVE_PCIE_3 163
#define X1E80100_SLAVE_PCIE_4 164
#define X1E80100_SLAVE_PCIE_5 165
#define X1E80100_SLAVE_PCIE_6A 166
#define X1E80100_SLAVE_PCIE_6B 167
#define X1E80100_SLAVE_DDR_PERF_MODE 168
#define X1E80100_SLAVE_PCIE_NORTH 169
#define X1E80100_SLAVE_PCIE_SOUTH 170
#define X1E80100_SLAVE_USB_NOC_SNOC 171
#define X1E80100_SLAVE_AGGRE_USB_NORTH 172
#define X1E80100_SLAVE_AGGRE_USB_SOUTH 173
#define X1E80100_SLAVE_LLCC_PCIE 174
#define X1E80100_SLAVE_EBI1_PCIE 175
#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE 176
#define X1E80100_SLAVE_PCIE_NORTH_PCIE 177
#define X1E80100_SLAVE_PCIE_SOUTH_PCIE 178
#endif

149
include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h Normal file
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@@ -0,0 +1,149 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KAANAPALI_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_KAANAPALI_H
#define MASTER_QSPI_0 0
#define MASTER_CRYPTO 1
#define MASTER_QUP_1 2
#define MASTER_SDCC_4 3
#define MASTER_UFS_MEM 4
#define MASTER_USB3 5
#define MASTER_QUP_2 6
#define MASTER_QUP_3 7
#define MASTER_QUP_4 8
#define MASTER_IPA 9
#define MASTER_SOCCP_PROC 10
#define MASTER_SP 11
#define MASTER_QDSS_ETR 12
#define MASTER_QDSS_ETR_1 13
#define MASTER_SDCC_2 14
#define SLAVE_A1NOC_SNOC 15
#define SLAVE_A2NOC_SNOC 16
#define MASTER_QUP_CORE_0 0
#define MASTER_QUP_CORE_1 1
#define MASTER_QUP_CORE_2 2
#define MASTER_QUP_CORE_3 3
#define MASTER_QUP_CORE_4 4
#define SLAVE_QUP_CORE_0 5
#define SLAVE_QUP_CORE_1 6
#define SLAVE_QUP_CORE_2 7
#define SLAVE_QUP_CORE_3 8
#define SLAVE_QUP_CORE_4 9
#define MASTER_CNOC_CFG 0
#define SLAVE_AHB2PHY_SOUTH 1
#define SLAVE_AHB2PHY_NORTH 2
#define SLAVE_CAMERA_CFG 3
#define SLAVE_CLK_CTL 4
#define SLAVE_CRYPTO_0_CFG 5
#define SLAVE_DISPLAY_CFG 6
#define SLAVE_EVA_CFG 7
#define SLAVE_GFX3D_CFG 8
#define SLAVE_I2C 9
#define SLAVE_I3C_IBI0_CFG 10
#define SLAVE_I3C_IBI1_CFG 11
#define SLAVE_IMEM_CFG 12
#define SLAVE_IPC_ROUTER_CFG 13
#define SLAVE_CNOC_MSS 14
#define SLAVE_PCIE_CFG 15
#define SLAVE_PRNG 16
#define SLAVE_QDSS_CFG 17
#define SLAVE_QSPI_0 18
#define SLAVE_QUP_1 19
#define SLAVE_QUP_2 20
#define SLAVE_QUP_3 21
#define SLAVE_QUP_4 22
#define SLAVE_SDCC_2 23
#define SLAVE_SDCC_4 24
#define SLAVE_SPSS_CFG 25
#define SLAVE_TCSR 26
#define SLAVE_TLMM 27
#define SLAVE_UFS_MEM_CFG 28
#define SLAVE_USB3 29
#define SLAVE_VENUS_CFG 30
#define SLAVE_VSENSE_CTRL_CFG 31
#define SLAVE_CNOC_MNOC_CFG 32
#define SLAVE_PCIE_ANOC_CFG 33
#define SLAVE_QDSS_STM 34
#define SLAVE_TCU 35
#define MASTER_GEM_NOC_CNOC 0
#define MASTER_GEM_NOC_PCIE_SNOC 1
#define SLAVE_AOSS 2
#define SLAVE_IPA_CFG 3
#define SLAVE_IPC_ROUTER_FENCE 4
#define SLAVE_SOCCP 5
#define SLAVE_TME_CFG 6
#define SLAVE_APPSS 7
#define SLAVE_CNOC_CFG 8
#define SLAVE_DDRSS_CFG 9
#define SLAVE_BOOT_IMEM 10
#define SLAVE_IMEM 11
#define SLAVE_PCIE_0 12
#define MASTER_GPU_TCU 0
#define MASTER_SYS_TCU 1
#define MASTER_APPSS_PROC 2
#define MASTER_GFX3D 3
#define MASTER_LPASS_GEM_NOC 4
#define MASTER_MSS_PROC 5
#define MASTER_MNOC_HF_MEM_NOC 6
#define MASTER_MNOC_SF_MEM_NOC 7
#define MASTER_COMPUTE_NOC 8
#define MASTER_ANOC_PCIE_GEM_NOC 9
#define MASTER_QPACE 10
#define MASTER_SNOC_SF_MEM_NOC 11
#define MASTER_WLAN_Q6 12
#define MASTER_GIC 13
#define SLAVE_GEM_NOC_CNOC 14
#define SLAVE_LLCC 15
#define SLAVE_MEM_NOC_PCIE_SNOC 16
#define MASTER_LPIAON_NOC 0
#define SLAVE_LPASS_GEM_NOC 1
#define MASTER_LPASS_LPINOC 0
#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1
#define MASTER_LPASS_PROC 0
#define SLAVE_LPICX_NOC_LPIAON_NOC 1
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
#define MASTER_CAMNOC_HF 0
#define MASTER_CAMNOC_NRT_ICP_SF 1
#define MASTER_CAMNOC_RT_CDM_SF 2
#define MASTER_CAMNOC_SF 3
#define MASTER_MDP 4
#define MASTER_MDSS_DCP 5
#define MASTER_CDSP_HCP 6
#define MASTER_VIDEO_CV_PROC 7
#define MASTER_VIDEO_EVA 8
#define MASTER_VIDEO_MVP 9
#define MASTER_VIDEO_V_PROC 10
#define MASTER_CNOC_MNOC_CFG 11
#define SLAVE_MNOC_HF_MEM_NOC 12
#define SLAVE_MNOC_SF_MEM_NOC 13
#define SLAVE_SERVICE_MNOC 14
#define MASTER_CDSP_PROC 0
#define SLAVE_CDSP_MEM_NOC 1
#define MASTER_PCIE_ANOC_CFG 0
#define MASTER_PCIE_0 1
#define SLAVE_ANOC_PCIE_GEM_NOC 2
#define SLAVE_SERVICE_PCIE_ANOC 3
#define MASTER_A1NOC_SNOC 0
#define MASTER_A2NOC_SNOC 1
#define MASTER_APSS_NOC 2
#define MASTER_CNOC_SNOC 3
#define SLAVE_SNOC_GEM_NOC_SF 4
#endif

2
include/dt-bindings/interconnect/qcom,sdx75.h
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@@ -6,9 +6,7 @@
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
#define MASTER_QPIC_CORE 0
#define MASTER_QUP_CORE_0 1
#define SLAVE_QPIC_CORE 2
#define SLAVE_QUP_CORE_0 3
#define MASTER_LLCC 0

2
include/linux/interconnect.h
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@@ -16,7 +16,7 @@
#define MBps_to_icc(x) ((x) * 1000)
#define GBps_to_icc(x) ((x) * 1000 * 1000)
#define bps_to_icc(x) (1)
#define kbps_to_icc(x) ((x) / 8 + ((x) % 8 ? 1 : 0))
#define kbps_to_icc(x) (((x) + 7) / 8)
#define Mbps_to_icc(x) ((x) * 1000 / 8)
#define Gbps_to_icc(x) ((x) * 1000 * 1000 / 8)