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arm64: dts: qcom: stop using snps,dw-pcie falback

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Qualcomm PCIe devices are not really compatible with the snps,dw-pcie.
Unlike the generic IP core, they have special requirements regarding
enabling clocks, toggling resets, using the PHY, etc.

This is not to mention that platform snps-dw-pcie driver expects to find
two IRQs declared, while Qualcomm platforms use just one.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220506152107.1527552-6-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov
2022-05-06 18:21:04 +03:00
committed by Bjorn Andersson
parent ca1ce7207e
commit 3e4fec3bc8
2 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@@ -1297,7 +1297,7 @@ glink-edge {
};
pcie: pci@10000000 {
compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
compatible = "qcom,pcie-qcs404";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
<0x07780000 0x2000>,

6
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@@ -1792,7 +1792,7 @@ mmss_noc: interconnect@1740000 {
};
pcie0: pci@1c00000 {
compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
@@ -1893,7 +1893,7 @@ pcie0_lane: phy@1c06200 {
};
pcie1: pci@1c08000 {
compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
<0 0x40000f20 0 0xa8>,
@@ -2001,7 +2001,7 @@ pcie1_lane: phy@1c0e200 {
};
pcie2: pci@1c10000 {
compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c10000 0 0x3000>,
<0 0x64000000 0 0xf1d>,
<0 0x64000f20 0 0xa8>,