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drm/amd/display: Update VRR info packet to support 12-bit refresh rates

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[Why]
VRR info packet previously only supported up to 10-bit refresh rate values
limiting the range of FreeSync minimum and maximum refresh rates that
could be encoded.

[How]
Expanded the bit masking in PB11/PB12 from 2 to 4 bits to capture bits
11:8 of the minimum and maximum FreeSync refresh rates, enabling the VRR
info packet to encode 12-bit refresh rate values.

Reviewed-by: Anthony Koo <anthony.koo@amd.com>
Signed-off-by: Harry VanZyllDeJong <hvanzyll@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry VanZyllDeJong
2026-07-15 14:58:42 -04:00
committed by Alex Deucher
parent 807d6345bc
commit 3df68ac6a7
1 changed files with 4 additions and 4 deletions
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8
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
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@@ -684,11 +684,11 @@ static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
/* PB8 = FreeSync Maximum refresh rate (Hz) */
infopacket->sb[8] = max_refresh & 0xFF;
/* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 9:8 */
infopacket->sb[11] = (min_programmed >> 8) & 0x03;
/* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 11:8 */
infopacket->sb[11] = (min_programmed >> 8) & 0x0F;
/* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 9:8 */
infopacket->sb[12] = (max_refresh >> 8) & 0x03;
/* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 11:8 */
infopacket->sb[12] = (max_refresh >> 8) & 0x0F;
/* PB16 : Reserved bits 7:1, FixedRate bit 0 */
infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0;