mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-04-10 14:48:19 -04:00
Code Issues Packages Projects Releases Wiki Activity

clk: qcom: rpmh: Update the clock suffix for Glymur

Browse Source 
The current RPMh VRM clock definitions do not accurately represent the
hardware mapping of these clocks. While there is no functional impact,
this update aligns the definitions with the hardware convention by adding
the appropriate suffix to indicate the clock divider and the E0 variant
for the C3A_E0, C4A_E0, C5A_E0, and C8A_E0 resources on Glymur.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251209-gcc_kaanapali-v3-v5-1-3af118262289@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Taniya Das
2025-12-09 14:19:24 +05:30
committed by Bjorn Andersson
parent 8f0b4cce44
commit 3dadc1dc5e
1 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/clk/qcom/clk-rpmh.c
View File

@@ -390,10 +390,10 @@ DEFINE_CLK_RPMH_VRM(clk7, _a4, "clka7", 4);
DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2);
DEFINE_CLK_RPMH_VRM(clk3, _a, "C3A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk4, _a, "C4A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk5, _a, "C5A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk8, _a, "C8A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk3, _a1_e0, "C3A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk4, _a1_e0, "C4A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk5, _a1_e0, "C5A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk8, _a1_e0, "C8A_E0", 1);
DEFINE_CLK_RPMH_BCM(ce, "CE0");
DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
@@ -888,12 +888,12 @@ static const struct clk_rpmh_desc clk_rpmh_sm8750 = {
static struct clk_hw *glymur_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_clk4_a.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_clk5_a.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_clk3_a1_e0.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a1_e0_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_clk4_a1_e0.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_e0_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_clk5_a1_e0.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a1_e0_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_glymur = {