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iio: dac: ad3552r-hs: add debugfs reg access

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Add debugfs register access.

Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Reviewed-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20250319-wip-bl-ad3552r-fixes-v3-1-9975b38c0082@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Angelo Dureghello
2025-03-19 16:45:31 +01:00
committed by Jonathan Cameron
parent d9848cb632
commit 3c8fd200a7
3 changed files with 25 additions and 0 deletions
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4
drivers/iio/dac/ad3552r-common.c
View File

@@ -43,6 +43,7 @@ const struct ad3552r_model_data ad3541r_model_data = {
.num_ranges = ARRAY_SIZE(ad3542r_ch_ranges),
.requires_output_range = true,
.num_spi_data_lanes = 2,
.max_reg_addr = 0x46,
};
EXPORT_SYMBOL_NS_GPL(ad3541r_model_data, "IIO_AD3552R");
@@ -54,6 +55,7 @@ const struct ad3552r_model_data ad3542r_model_data = {
.num_ranges = ARRAY_SIZE(ad3542r_ch_ranges),
.requires_output_range = true,
.num_spi_data_lanes = 2,
.max_reg_addr = 0x49,
};
EXPORT_SYMBOL_NS_GPL(ad3542r_model_data, "IIO_AD3552R");
@@ -65,6 +67,7 @@ const struct ad3552r_model_data ad3551r_model_data = {
.num_ranges = ARRAY_SIZE(ad3552r_ch_ranges),
.requires_output_range = false,
.num_spi_data_lanes = 4,
.max_reg_addr = 0x46,
};
EXPORT_SYMBOL_NS_GPL(ad3551r_model_data, "IIO_AD3552R");
@@ -76,6 +79,7 @@ const struct ad3552r_model_data ad3552r_model_data = {
.num_ranges = ARRAY_SIZE(ad3552r_ch_ranges),
.requires_output_range = false,
.num_spi_data_lanes = 4,
.max_reg_addr = 0x49,
};
EXPORT_SYMBOL_NS_GPL(ad3552r_model_data, "IIO_AD3552R");

20
drivers/iio/dac/ad3552r-hs.c
View File

@@ -464,6 +464,25 @@ static int ad3552r_hs_setup_custom_gain(struct ad3552r_hs_state *st,
gain, 1);
}
static int ad3552r_hs_reg_access(struct iio_dev *indio_dev, unsigned int reg,
unsigned int writeval, unsigned int *readval)
{
struct ad3552r_hs_state *st = iio_priv(indio_dev);
if (reg > st->model_data->max_reg_addr)
return -EINVAL;
/*
* There are 8, 16 or 24 bit registers, but HDL supports only reading 8
* or 16 bit data, not 24. So, also to avoid to check any proper read
* alignment, supporting only 8-bit readings here.
*/
if (readval)
return ad3552r_hs_reg_read(st, reg, readval, 1);
return st->data->bus_reg_write(st->back, reg, writeval, 1);
}
static int ad3552r_hs_setup(struct ad3552r_hs_state *st)
{
u16 id;
@@ -639,6 +658,7 @@ static const struct iio_chan_spec ad3552r_hs_channels[] = {
static const struct iio_info ad3552r_hs_info = {
.read_raw = &ad3552r_hs_read_raw,
.write_raw = &ad3552r_hs_write_raw,
.debugfs_reg_access = &ad3552r_hs_reg_access,
};
static int ad3552r_hs_probe(struct platform_device *pdev)

1
drivers/iio/dac/ad3552r.h
View File

@@ -156,6 +156,7 @@ struct ad3552r_model_data {
int num_ranges;
bool requires_output_range;
int num_spi_data_lanes;
int max_reg_addr;
};
struct ad3552r_ch_data {