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arm64: dts: mediatek: mt8188: Add CPU performance controller for CPUFreq

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Add performance controller node and performance-domains properties for
CPUFreq support on MT8188 SoC.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Fei Shao <fshao@chromium.org>
Link: https://lore.kernel.org/r/20240911143429.850071-4-fshao@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Fei Shao
2024-09-11 22:33:56 +08:00
committed by AngeloGioacchino Del Regno
parent ec1a37b3cd
commit 3bbae49ea0
1 changed files with 14 additions and 0 deletions
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14
arch/arm64/boot/dts/mediatek/mt8188.dtsi
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@@ -41,6 +41,7 @@ cpu0: cpu@0 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
@@ -59,6 +60,7 @@ cpu1: cpu@100 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
@@ -77,6 +79,7 @@ cpu2: cpu@200 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
@@ -95,6 +98,7 @@ cpu3: cpu@300 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
@@ -113,6 +117,7 @@ cpu4: cpu@400 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
@@ -131,6 +136,7 @@ cpu5: cpu@500 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
@@ -149,6 +155,7 @@ cpu6: cpu@600 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
#cooling-cells = <2>;
};
@@ -167,6 +174,7 @@ cpu7: cpu@700 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
#cooling-cells = <2>;
};
@@ -881,6 +889,12 @@ soc {
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
ranges;
performance: performance-controller@11bc10 {
compatible = "mediatek,cpufreq-hw";
reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
#performance-domain-cells = <1>;
};
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;