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drm/msm/dsi/phy: Define PHY_CMN_CTRL_0 bitfields

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Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
masks and shifts and make the code a bit more readable.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/657818/
Link: https://lore.kernel.org/r/20250610-b4-sm8750-display-v6-7-ee633e3ddbff@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Krzysztof Kozlowski
2025-06-10 16:05:45 +02:00
committed by Dmitry Baryshkov
parent b63f008f39
commit 3bb6433ecb
2 changed files with 21 additions and 6 deletions
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16
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
View File

@@ -385,18 +385,23 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
{
u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
u32 data;
data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
data &= ~DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB;
writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
writel(data & ~BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
ndelay(250);
}
static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
{
u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
u32 data;
data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
data |= DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB;
writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
writel(data | BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
writel(0xc0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
ndelay(250);
}
@@ -1036,7 +1041,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
}
/* de-assert digital and pll power down */
data = BIT(6) | BIT(5);
data = DSI_7nm_PHY_CMN_CTRL_0_DIGTOP_PWRDN_B |
DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB;
writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
/* Assert PLL core reset */

11
drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
View File

@@ -22,7 +22,16 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<reg32 offset="0x00018" name="GLBL_CTRL"/>
<reg32 offset="0x0001c" name="RBUF_CTRL"/>
<reg32 offset="0x00020" name="VREG_CTRL_0"/>
<reg32 offset="0x00024" name="CTRL_0"/>
<reg32 offset="0x00024" name="CTRL_0">
<bitfield name="CLKSL_SHUTDOWNB" pos="7" type="boolean"/>
<bitfield name="DIGTOP_PWRDN_B" pos="6" type="boolean"/>
<bitfield name="PLL_SHUTDOWNB" pos="5" type="boolean"/>
<bitfield name="DLN3_SHUTDOWNB" pos="4" type="boolean"/>
<bitfield name="DLN2_SHUTDOWNB" pos="3" type="boolean"/>
<bitfield name="CLK_SHUTDOWNB" pos="2" type="boolean"/>
<bitfield name="DLN1_SHUTDOWNB" pos="1" type="boolean"/>
<bitfield name="DLN0_SHUTDOWNB" pos="0" type="boolean"/>
</reg32>
<reg32 offset="0x00028" name="CTRL_1"/>
<reg32 offset="0x0002c" name="CTRL_2"/>
<reg32 offset="0x00030" name="CTRL_3"/>