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drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers

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Add register definitions for SFF_CTL and CFF_CTL registers. Name them as
LNL_SFF_CTL and LNL_CFF_CTL.

v2: use _MMIO_TRANS instead of _MMIO_TRANS2

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213064804.2077127-5-jouni.hogander@intel.com
This commit is contained in:
Jouni Högander
2025-02-13 08:47:55 +02:00
parent 005010f1f7
commit 3b5bf853e3
1 changed files with 10 additions and 0 deletions
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10
drivers/gpu/drm/i915/display/intel_psr_regs.h
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@@ -251,6 +251,16 @@
#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
#define _LNL_SFF_CTL_A 0x60918
#define _LNL_SFF_CTL_B 0x61918
#define LNL_SFF_CTL(tran) _MMIO_TRANS(tran, _LNL_SFF_CTL_A, _LNL_SFF_CTL_B)
#define LNL_SFF_CTL_SF_SINGLE_FULL_FRAME REG_BIT(1)
#define _LNL_CFF_CTL_A 0x6091c
#define _LNL_CFF_CTL_B 0x6191c
#define LNL_CFF_CTL(tran) _MMIO_TRANS(tran, _LNL_CFF_CTL_A, _LNL_CFF_CTL_B)
#define LNL_CFF_CTL_SF_CONTINUOUS_FULL_FRAME REG_BIT(1)
/* PSR2 Early transport */
#define _PIPE_SRCSZ_ERLY_TPT_A 0x70074
#define _PIPE_SRCSZ_ERLY_TPT_B 0x71074