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dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg

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The description of second IO address is a bit confusing.  It is supposed
to be the MCC range which contains the slew rate registers, not the slew
rate register base.  The Linux driver then accesses slew rate register
with hard-coded offset (0xa000).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230302155255.857065-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Krzysztof Kozlowski
2023-03-02 16:52:55 +01:00
committed by Linus Walleij
parent 6cf103bc03
commit 3abe84ea06
3 changed files with 3 additions and 3 deletions
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2
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
View File

@@ -20,7 +20,7 @@ properties:
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI pins SLEW registers
- description: LPASS LPI MCC registers
clocks:
items:

2
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
View File

@@ -20,7 +20,7 @@ properties:
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI pins SLEW registers
- description: LPASS LPI MCC registers
clocks:
items:

2
Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml
View File

@@ -21,7 +21,7 @@ properties:
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI pins SLEW registers
- description: LPASS LPI MCC registers
clocks:
items: