mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-07 13:57:54 -04:00
Merge tag 'samsung-clk-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clock driver updates from Krzysztof Kozlowski: - Add Samsung ExynosAutov920 CPU cluster CL0, CL1 and CL2 clock controllers - Fix Samsung ExynosAutov920 HSI1 USBDRD clock parents - Minor cleanup for Samsung Exynos4 clk drivers * tag 'samsung-clk-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: correct clock summary for hsi1 block clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition clk: samsung: exynosautov920: add cpucl1/2 clock support dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions clk: samsung: exynosautov920: add cpucl0 clock support dt-bindings: clock: exynosautov920: add cpucl0 clock definitions clk: samsung: Use samsung CCF common function
This commit is contained in:
Stephen Boyd
@@ -8,6 +8,7 @@ title: Samsung ExynosAuto v920 SoC clock controller
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maintainers:
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- Sunyeal Hong <sunyeal.hong@samsung.com>
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- Shin Son <shin.son@samsung.com>
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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@@ -32,6 +33,9 @@ properties:
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compatible:
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enum:
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- samsung,exynosautov920-cmu-top
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- samsung,exynosautov920-cmu-cpucl0
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- samsung,exynosautov920-cmu-cpucl1
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- samsung,exynosautov920-cmu-cpucl2
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- samsung,exynosautov920-cmu-peric0
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- samsung,exynosautov920-cmu-peric1
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- samsung,exynosautov920-cmu-misc
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@@ -69,6 +73,71 @@ allOf:
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items:
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- const: oscclk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynosautov920-cmu-cpucl0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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- description: CMU_CPUCL0 SWITCH clock (from CMU_TOP)
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- description: CMU_CPUCL0 CLUSTER clock (from CMU_TOP)
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- description: CMU_CPUCL0 DBG clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: switch
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- const: cluster
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- const: dbg
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynosautov920-cmu-cpucl1
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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- description: CMU_CPUCL1 SWITCH clock (from CMU_TOP)
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- description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: switch
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- const: cluster
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynosautov920-cmu-cpucl2
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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- description: CMU_CPUCL2 SWITCH clock (from CMU_TOP)
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- description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: switch
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- const: cluster
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- if:
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properties:
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compatible:
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@@ -1269,6 +1269,45 @@ static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
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CPUCLK_LAYOUT_E4210, e4412_armclk_d),
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};
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static const struct samsung_cmu_info cmu_info_exynos4 __initconst = {
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.mux_clks = exynos4_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(exynos4_mux_clks),
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.div_clks = exynos4_div_clks,
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.nr_div_clks = ARRAY_SIZE(exynos4_div_clks),
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.gate_clks = exynos4_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(exynos4_gate_clks),
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.fixed_factor_clks = exynos4_fixed_factor_clks,
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.nr_fixed_factor_clks = ARRAY_SIZE(exynos4_fixed_factor_clks),
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.fixed_clks = exynos4_fixed_rate_clks,
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.nr_fixed_clks = ARRAY_SIZE(exynos4_fixed_rate_clks),
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};
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static const struct samsung_cmu_info cmu_info_exynos4210 __initconst = {
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.mux_clks = exynos4210_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(exynos4210_mux_clks),
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.div_clks = exynos4210_div_clks,
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.nr_div_clks = ARRAY_SIZE(exynos4210_div_clks),
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.gate_clks = exynos4210_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(exynos4210_gate_clks),
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.fixed_factor_clks = exynos4210_fixed_factor_clks,
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.nr_fixed_factor_clks = ARRAY_SIZE(exynos4210_fixed_factor_clks),
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.fixed_clks = exynos4210_fixed_rate_clks,
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.nr_fixed_clks = ARRAY_SIZE(exynos4210_fixed_rate_clks),
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.cpu_clks = exynos4210_cpu_clks,
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.nr_cpu_clks = ARRAY_SIZE(exynos4210_cpu_clks),
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};
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static const struct samsung_cmu_info cmu_info_exynos4x12 __initconst = {
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.mux_clks = exynos4x12_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(exynos4x12_mux_clks),
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.div_clks = exynos4x12_div_clks,
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.nr_div_clks = ARRAY_SIZE(exynos4x12_div_clks),
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.gate_clks = exynos4x12_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(exynos4x12_gate_clks),
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.fixed_factor_clks = exynos4x12_fixed_factor_clks,
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.nr_fixed_factor_clks = ARRAY_SIZE(exynos4x12_fixed_factor_clks),
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};
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/* register exynos4 clocks */
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static void __init exynos4_clk_init(struct device_node *np,
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enum exynos4_soc soc)
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@@ -1322,41 +1361,12 @@ static void __init exynos4_clk_init(struct device_node *np,
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ARRAY_SIZE(exynos4x12_plls));
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}
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samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
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ARRAY_SIZE(exynos4_fixed_rate_clks));
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samsung_clk_register_mux(ctx, exynos4_mux_clks,
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ARRAY_SIZE(exynos4_mux_clks));
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samsung_clk_register_div(ctx, exynos4_div_clks,
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ARRAY_SIZE(exynos4_div_clks));
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samsung_clk_register_gate(ctx, exynos4_gate_clks,
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ARRAY_SIZE(exynos4_gate_clks));
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samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
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ARRAY_SIZE(exynos4_fixed_factor_clks));
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samsung_cmu_register_clocks(ctx, &cmu_info_exynos4);
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if (exynos4_soc == EXYNOS4210) {
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samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
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ARRAY_SIZE(exynos4210_fixed_rate_clks));
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samsung_clk_register_mux(ctx, exynos4210_mux_clks,
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ARRAY_SIZE(exynos4210_mux_clks));
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samsung_clk_register_div(ctx, exynos4210_div_clks,
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ARRAY_SIZE(exynos4210_div_clks));
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samsung_clk_register_gate(ctx, exynos4210_gate_clks,
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ARRAY_SIZE(exynos4210_gate_clks));
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samsung_clk_register_fixed_factor(ctx,
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exynos4210_fixed_factor_clks,
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ARRAY_SIZE(exynos4210_fixed_factor_clks));
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samsung_clk_register_cpu(ctx, exynos4210_cpu_clks,
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ARRAY_SIZE(exynos4210_cpu_clks));
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samsung_cmu_register_clocks(ctx, &cmu_info_exynos4210);
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} else {
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samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
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ARRAY_SIZE(exynos4x12_mux_clks));
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samsung_clk_register_div(ctx, exynos4x12_div_clks,
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ARRAY_SIZE(exynos4x12_div_clks));
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samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
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ARRAY_SIZE(exynos4x12_gate_clks));
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samsung_clk_register_fixed_factor(ctx,
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exynos4x12_fixed_factor_clks,
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ARRAY_SIZE(exynos4x12_fixed_factor_clks));
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samsung_cmu_register_clocks(ctx, &cmu_info_exynos4x12);
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if (soc == EXYNOS4412)
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samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
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ARRAY_SIZE(exynos4412_cpu_clks));
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@@ -18,6 +18,9 @@
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/* NOTE: Must be equal to the last clock ID increased by one */
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#define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
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#define CLKS_NR_CPUCL0 (CLK_DOUT_CPUCL0_NOCP + 1)
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#define CLKS_NR_CPUCL1 (CLK_DOUT_CPUCL1_NOCP + 1)
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#define CLKS_NR_CPUCL2 (CLK_DOUT_CPUCL2_NOCP + 1)
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#define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1)
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#define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1)
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#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
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@@ -1005,6 +1008,339 @@ static void __init exynosautov920_cmu_top_init(struct device_node *np)
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CLK_OF_DECLARE(exynosautov920_cmu_top, "samsung,exynosautov920-cmu-top",
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exynosautov920_cmu_top_init);
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/* ---- CMU_CPUCL0 --------------------------------------------------------- */
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/* Register Offset definitions for CMU_CPUCL0 (0x1EC00000) */
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#define PLL_LOCKTIME_PLL_CPUCL0 0x0000
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#define PLL_CON0_PLL_CPUCL0 0x0100
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#define PLL_CON1_PLL_CPUCL0 0x0104
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#define PLL_CON3_PLL_CPUCL0 0x010c
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#define PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER 0x0600
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#define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0610
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#define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0620
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#define CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER 0x1000
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#define CLK_CON_MUX_MUX_CLK_CPUCL0_CORE 0x1004
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#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800
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#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1804
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#define CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK 0x1808
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#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK 0x180c
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#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810
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#define CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC 0x181c
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#define CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG 0x1820
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#define CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP 0x1824
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static const unsigned long cpucl0_clk_regs[] __initconst = {
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PLL_LOCKTIME_PLL_CPUCL0,
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PLL_CON0_PLL_CPUCL0,
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PLL_CON1_PLL_CPUCL0,
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PLL_CON3_PLL_CPUCL0,
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PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER,
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PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER,
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PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
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CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER,
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CLK_CON_MUX_MUX_CLK_CPUCL0_CORE,
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CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
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CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK,
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CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK,
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CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK,
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CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK,
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CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC,
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CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG,
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CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP,
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};
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/* List of parent clocks for Muxes in CMU_CPUCL0 */
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PNAME(mout_pll_cpucl0_p) = { "oscclk", "fout_cpucl0_pll" };
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PNAME(mout_cpucl0_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl0_cluster" };
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PNAME(mout_cpucl0_dbg_user_p) = { "oscclk", "dout_clkcmu_cpucl0_dbg" };
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PNAME(mout_cpucl0_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl0_switch" };
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PNAME(mout_cpucl0_cluster_p) = { "oscclk", "mout_cpucl0_cluster_user",
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"mout_cpucl0_switch_user"};
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PNAME(mout_cpucl0_core_p) = { "oscclk", "mout_pll_cpucl0",
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"mout_cpucl0_switch_user"};
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static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = {
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PLL_35XX_RATE(38400000U, 2400000000U, 250, 4, 0),
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PLL_35XX_RATE(38400000U, 2304000000U, 240, 4, 0),
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PLL_35XX_RATE(38400000U, 2208000000U, 230, 4, 0),
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PLL_35XX_RATE(38400000U, 2112000000U, 220, 4, 0),
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PLL_35XX_RATE(38400000U, 2016000000U, 210, 4, 0),
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PLL_35XX_RATE(38400000U, 1824000000U, 190, 4, 0),
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PLL_35XX_RATE(38400000U, 1680000000U, 175, 4, 0),
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PLL_35XX_RATE(38400000U, 1344000000U, 140, 4, 0),
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PLL_35XX_RATE(38400000U, 1152000000U, 120, 4, 0),
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PLL_35XX_RATE(38400000U, 576000000U, 120, 4, 1),
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PLL_35XX_RATE(38400000U, 288000000U, 120, 4, 2),
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};
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static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = {
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/* CMU_CPUCL0_PURECLKCOMP */
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PLL(pll_531x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
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PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, cpu_pll_rates),
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};
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static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = {
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MUX(CLK_MOUT_PLL_CPUCL0, "mout_pll_cpucl0", mout_pll_cpucl0_p,
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PLL_CON0_PLL_CPUCL0, 4, 1),
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MUX(CLK_MOUT_CPUCL0_CLUSTER_USER, "mout_cpucl0_cluster_user", mout_cpucl0_cluster_user_p,
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PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER, 4, 1),
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MUX(CLK_MOUT_CPUCL0_DBG_USER, "mout_cpucl0_dbg_user", mout_cpucl0_dbg_user_p,
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PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1),
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MUX(CLK_MOUT_CPUCL0_SWITCH_USER, "mout_cpucl0_switch_user", mout_cpucl0_switch_user_p,
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PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1),
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MUX(CLK_MOUT_CPUCL0_CLUSTER, "mout_cpucl0_cluster", mout_cpucl0_cluster_p,
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CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER, 0, 2),
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MUX(CLK_MOUT_CPUCL0_CORE, "mout_cpucl0_core", mout_cpucl0_core_p,
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CLK_CON_MUX_MUX_CLK_CPUCL0_CORE, 0, 2),
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};
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static const struct samsung_div_clock cpucl0_div_clks[] __initconst = {
|
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DIV(CLK_DOUT_CLUSTER0_ACLK, "dout_cluster0_aclk",
|
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"mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4),
|
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DIV(CLK_DOUT_CLUSTER0_ATCLK, "dout_cluster0_atclk",
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"mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4),
|
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DIV(CLK_DOUT_CLUSTER0_MPCLK, "dout_cluster0_mpclk",
|
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"mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK, 0, 4),
|
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DIV(CLK_DOUT_CLUSTER0_PCLK, "dout_cluster0_pclk",
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"mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK, 0, 4),
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DIV(CLK_DOUT_CLUSTER0_PERIPHCLK, "dout_cluster0_periphclk",
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"mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4),
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DIV(CLK_DOUT_CPUCL0_DBG_NOC, "dout_cpucl0_dbg_noc",
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"mout_cpucl0_dbg_user", CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC, 0, 3),
|
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DIV(CLK_DOUT_CPUCL0_DBG_PCLKDBG, "dout_cpucl0_dbg_pclkdbg",
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"mout_cpucl0_dbg_user", CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, 0, 3),
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DIV(CLK_DOUT_CPUCL0_NOCP, "dout_cpucl0_nocp",
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"mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP, 0, 4),
|
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};
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static const struct samsung_cmu_info cpucl0_cmu_info __initconst = {
|
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.pll_clks = cpucl0_pll_clks,
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.nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks),
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.mux_clks = cpucl0_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks),
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.div_clks = cpucl0_div_clks,
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.nr_div_clks = ARRAY_SIZE(cpucl0_div_clks),
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.nr_clk_ids = CLKS_NR_CPUCL0,
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.clk_regs = cpucl0_clk_regs,
|
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.nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs),
|
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.clk_name = "cpucl0",
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};
|
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|
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static void __init exynosautov920_cmu_cpucl0_init(struct device_node *np)
|
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{
|
||||
exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info);
|
||||
}
|
||||
|
||||
/* Register CMU_CPUCL0 early, as CPU clocks should be available ASAP */
|
||||
CLK_OF_DECLARE(exynosautov920_cmu_cpucl0, "samsung,exynosautov920-cmu-cpucl0",
|
||||
exynosautov920_cmu_cpucl0_init);
|
||||
|
||||
/* ---- CMU_CPUCL1 --------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_CPUCL1 (0x1ED00000) */
|
||||
#define PLL_LOCKTIME_PLL_CPUCL1 0x0000
|
||||
#define PLL_CON0_PLL_CPUCL1 0x0100
|
||||
#define PLL_CON1_PLL_CPUCL1 0x0104
|
||||
#define PLL_CON3_PLL_CPUCL1 0x010c
|
||||
#define PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER 0x0600
|
||||
#define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
|
||||
|
||||
#define CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER 0x1000
|
||||
#define CLK_CON_MUX_MUX_CLK_CPUCL1_CORE 0x1004
|
||||
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1804
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK 0x1808
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK 0x180c
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
|
||||
#define CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP 0x181c
|
||||
|
||||
static const unsigned long cpucl1_clk_regs[] __initconst = {
|
||||
PLL_LOCKTIME_PLL_CPUCL1,
|
||||
PLL_CON0_PLL_CPUCL1,
|
||||
PLL_CON1_PLL_CPUCL1,
|
||||
PLL_CON3_PLL_CPUCL1,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
||||
CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER,
|
||||
CLK_CON_MUX_MUX_CLK_CPUCL1_CORE,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK,
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_CPUCL1 */
|
||||
PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
|
||||
PNAME(mout_cpucl1_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl1_cluster" };
|
||||
PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl1_switch" };
|
||||
PNAME(mout_cpucl1_cluster_p) = { "oscclk", "mout_cpucl1_cluster_user",
|
||||
"mout_cpucl1_switch_user"};
|
||||
PNAME(mout_cpucl1_core_p) = { "oscclk", "mout_pll_cpucl1",
|
||||
"mout_cpucl1_switch_user"};
|
||||
|
||||
static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
|
||||
/* CMU_CPUCL1_PURECLKCOMP */
|
||||
PLL(pll_531x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates),
|
||||
};
|
||||
|
||||
static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p,
|
||||
PLL_CON0_PLL_CPUCL1, 4, 1),
|
||||
MUX(CLK_MOUT_CPUCL1_CLUSTER_USER, "mout_cpucl1_cluster_user", mout_cpucl1_cluster_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER, 4, 1),
|
||||
MUX(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user", mout_cpucl1_switch_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1),
|
||||
MUX(CLK_MOUT_CPUCL1_CLUSTER, "mout_cpucl1_cluster", mout_cpucl1_cluster_p,
|
||||
CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER, 0, 2),
|
||||
MUX(CLK_MOUT_CPUCL1_CORE, "mout_cpucl1_core", mout_cpucl1_core_p,
|
||||
CLK_CON_MUX_MUX_CLK_CPUCL1_CORE, 0, 2),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
|
||||
DIV(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk",
|
||||
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4),
|
||||
DIV(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk",
|
||||
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4),
|
||||
DIV(CLK_DOUT_CLUSTER1_MPCLK, "dout_cluster1_mpclk",
|
||||
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK, 0, 4),
|
||||
DIV(CLK_DOUT_CLUSTER1_PCLK, "dout_cluster1_pclk",
|
||||
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK, 0, 4),
|
||||
DIV(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk",
|
||||
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4),
|
||||
DIV(CLK_DOUT_CPUCL1_NOCP, "dout_cpucl1_nocp",
|
||||
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP, 0, 4),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
|
||||
.pll_clks = cpucl1_pll_clks,
|
||||
.nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
|
||||
.mux_clks = cpucl1_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
|
||||
.div_clks = cpucl1_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
|
||||
.nr_clk_ids = CLKS_NR_CPUCL1,
|
||||
.clk_regs = cpucl1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
|
||||
.clk_name = "cpucl1",
|
||||
};
|
||||
|
||||
static void __init exynosautov920_cmu_cpucl1_init(struct device_node *np)
|
||||
{
|
||||
exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
|
||||
}
|
||||
|
||||
/* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */
|
||||
CLK_OF_DECLARE(exynosautov920_cmu_cpucl1, "samsung,exynosautov920-cmu-cpucl1",
|
||||
exynosautov920_cmu_cpucl1_init);
|
||||
|
||||
/* ---- CMU_CPUCL2 --------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_CPUCL2 (0x1EE00000) */
|
||||
#define PLL_LOCKTIME_PLL_CPUCL2 0x0000
|
||||
#define PLL_CON0_PLL_CPUCL2 0x0100
|
||||
#define PLL_CON1_PLL_CPUCL2 0x0104
|
||||
#define PLL_CON3_PLL_CPUCL2 0x010c
|
||||
#define PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER 0x0600
|
||||
#define PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER 0x0610
|
||||
|
||||
#define CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER 0x1000
|
||||
#define CLK_CON_MUX_MUX_CLK_CPUCL2_CORE 0x1004
|
||||
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK 0x1800
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK 0x1804
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK 0x1808
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK 0x180c
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK 0x1810
|
||||
#define CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP 0x181c
|
||||
|
||||
static const unsigned long cpucl2_clk_regs[] __initconst = {
|
||||
PLL_LOCKTIME_PLL_CPUCL2,
|
||||
PLL_CON0_PLL_CPUCL2,
|
||||
PLL_CON1_PLL_CPUCL2,
|
||||
PLL_CON3_PLL_CPUCL2,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER,
|
||||
CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER,
|
||||
CLK_CON_MUX_MUX_CLK_CPUCL2_CORE,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK,
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_CPUCL2 */
|
||||
PNAME(mout_pll_cpucl2_p) = { "oscclk", "fout_cpucl2_pll" };
|
||||
PNAME(mout_cpucl2_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl2_cluster" };
|
||||
PNAME(mout_cpucl2_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl2_switch" };
|
||||
PNAME(mout_cpucl2_cluster_p) = { "oscclk", "mout_cpucl2_cluster_user",
|
||||
"mout_cpucl2_switch_user"};
|
||||
PNAME(mout_cpucl2_core_p) = { "oscclk", "mout_pll_cpucl2",
|
||||
"mout_cpucl2_switch_user"};
|
||||
|
||||
static const struct samsung_pll_clock cpucl2_pll_clks[] __initconst = {
|
||||
/* CMU_CPUCL2_PURECLKCOMP */
|
||||
PLL(pll_531x, CLK_FOUT_CPUCL2_PLL, "fout_cpucl2_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_CPUCL2, PLL_CON3_PLL_CPUCL2, cpu_pll_rates),
|
||||
};
|
||||
|
||||
static const struct samsung_mux_clock cpucl2_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_PLL_CPUCL2, "mout_pll_cpucl2", mout_pll_cpucl2_p,
|
||||
PLL_CON0_PLL_CPUCL2, 4, 1),
|
||||
MUX(CLK_MOUT_CPUCL2_CLUSTER_USER, "mout_cpucl2_cluster_user", mout_cpucl2_cluster_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER, 4, 1),
|
||||
MUX(CLK_MOUT_CPUCL2_SWITCH_USER, "mout_cpucl2_switch_user", mout_cpucl2_switch_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, 4, 1),
|
||||
MUX(CLK_MOUT_CPUCL2_CLUSTER, "mout_cpucl2_cluster", mout_cpucl2_cluster_p,
|
||||
CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER, 0, 2),
|
||||
MUX(CLK_MOUT_CPUCL2_CORE, "mout_cpucl2_core", mout_cpucl2_core_p,
|
||||
CLK_CON_MUX_MUX_CLK_CPUCL2_CORE, 0, 2),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock cpucl2_div_clks[] __initconst = {
|
||||
DIV(CLK_DOUT_CLUSTER2_ACLK, "dout_cluster2_aclk",
|
||||
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK, 0, 4),
|
||||
DIV(CLK_DOUT_CLUSTER2_ATCLK, "dout_cluster2_atclk",
|
||||
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK, 0, 4),
|
||||
DIV(CLK_DOUT_CLUSTER2_MPCLK, "dout_cluster2_mpclk",
|
||||
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK, 0, 4),
|
||||
DIV(CLK_DOUT_CLUSTER2_PCLK, "dout_cluster2_pclk",
|
||||
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK, 0, 4),
|
||||
DIV(CLK_DOUT_CLUSTER2_PERIPHCLK, "dout_cluster2_periphclk",
|
||||
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK, 0, 4),
|
||||
DIV(CLK_DOUT_CPUCL2_NOCP, "dout_cpucl2_nocp",
|
||||
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP, 0, 4),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info cpucl2_cmu_info __initconst = {
|
||||
.pll_clks = cpucl2_pll_clks,
|
||||
.nr_pll_clks = ARRAY_SIZE(cpucl2_pll_clks),
|
||||
.mux_clks = cpucl2_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(cpucl2_mux_clks),
|
||||
.div_clks = cpucl2_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(cpucl2_div_clks),
|
||||
.nr_clk_ids = CLKS_NR_CPUCL2,
|
||||
.clk_regs = cpucl2_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(cpucl2_clk_regs),
|
||||
.clk_name = "cpucl2",
|
||||
};
|
||||
|
||||
static void __init exynosautov920_cmu_cpucl2_init(struct device_node *np)
|
||||
{
|
||||
exynos_arm64_register_cmu(NULL, np, &cpucl2_cmu_info);
|
||||
}
|
||||
|
||||
/* Register CMU_CPUCL2 early, as CPU clocks should be available ASAP */
|
||||
CLK_OF_DECLARE(exynosautov920_cmu_cpucl2, "samsung,exynosautov920-cmu-cpucl2",
|
||||
exynosautov920_cmu_cpucl2_init);
|
||||
|
||||
/* ---- CMU_PERIC0 --------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_PERIC0 (0x10800000) */
|
||||
@@ -1393,7 +1729,7 @@ static const unsigned long hsi1_clk_regs[] __initconst = {
|
||||
/* List of parent clocks for Muxes in CMU_HSI1 */
|
||||
PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"};
|
||||
PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" };
|
||||
PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" };
|
||||
PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_hsi1_usbdrd" };
|
||||
PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" };
|
||||
|
||||
static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {
|
||||
|
||||
@@ -162,6 +162,57 @@
|
||||
#define DOUT_CLKCMU_TAA_NOC 146
|
||||
#define DOUT_TCXO_DIV2 147
|
||||
|
||||
/* CMU_CPUCL0 */
|
||||
#define CLK_FOUT_CPUCL0_PLL 1
|
||||
|
||||
#define CLK_MOUT_PLL_CPUCL0 2
|
||||
#define CLK_MOUT_CPUCL0_CLUSTER_USER 3
|
||||
#define CLK_MOUT_CPUCL0_DBG_USER 4
|
||||
#define CLK_MOUT_CPUCL0_SWITCH_USER 5
|
||||
#define CLK_MOUT_CPUCL0_CLUSTER 6
|
||||
#define CLK_MOUT_CPUCL0_CORE 7
|
||||
|
||||
#define CLK_DOUT_CLUSTER0_ACLK 8
|
||||
#define CLK_DOUT_CLUSTER0_ATCLK 9
|
||||
#define CLK_DOUT_CLUSTER0_MPCLK 10
|
||||
#define CLK_DOUT_CLUSTER0_PCLK 11
|
||||
#define CLK_DOUT_CLUSTER0_PERIPHCLK 12
|
||||
#define CLK_DOUT_CPUCL0_DBG_NOC 13
|
||||
#define CLK_DOUT_CPUCL0_DBG_PCLKDBG 14
|
||||
#define CLK_DOUT_CPUCL0_NOCP 15
|
||||
|
||||
/* CMU_CPUCL1 */
|
||||
#define CLK_FOUT_CPUCL1_PLL 1
|
||||
|
||||
#define CLK_MOUT_PLL_CPUCL1 2
|
||||
#define CLK_MOUT_CPUCL1_CLUSTER_USER 3
|
||||
#define CLK_MOUT_CPUCL1_SWITCH_USER 4
|
||||
#define CLK_MOUT_CPUCL1_CLUSTER 5
|
||||
#define CLK_MOUT_CPUCL1_CORE 6
|
||||
|
||||
#define CLK_DOUT_CLUSTER1_ACLK 7
|
||||
#define CLK_DOUT_CLUSTER1_ATCLK 8
|
||||
#define CLK_DOUT_CLUSTER1_MPCLK 9
|
||||
#define CLK_DOUT_CLUSTER1_PCLK 10
|
||||
#define CLK_DOUT_CLUSTER1_PERIPHCLK 11
|
||||
#define CLK_DOUT_CPUCL1_NOCP 12
|
||||
|
||||
/* CMU_CPUCL2 */
|
||||
#define CLK_FOUT_CPUCL2_PLL 1
|
||||
|
||||
#define CLK_MOUT_PLL_CPUCL2 2
|
||||
#define CLK_MOUT_CPUCL2_CLUSTER_USER 3
|
||||
#define CLK_MOUT_CPUCL2_SWITCH_USER 4
|
||||
#define CLK_MOUT_CPUCL2_CLUSTER 5
|
||||
#define CLK_MOUT_CPUCL2_CORE 6
|
||||
|
||||
#define CLK_DOUT_CLUSTER2_ACLK 7
|
||||
#define CLK_DOUT_CLUSTER2_ATCLK 8
|
||||
#define CLK_DOUT_CLUSTER2_MPCLK 9
|
||||
#define CLK_DOUT_CLUSTER2_PCLK 10
|
||||
#define CLK_DOUT_CLUSTER2_PERIPHCLK 11
|
||||
#define CLK_DOUT_CPUCL2_NOCP 12
|
||||
|
||||
/* CMU_PERIC0 */
|
||||
#define CLK_MOUT_PERIC0_IP_USER 1
|
||||
#define CLK_MOUT_PERIC0_NOC_USER 2
|
||||
|
||||
Reference in New Issue
Block a user