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drm/amd/powerplay: enable gfxclk ds,dcefclk ds and fw dstate on navi10

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on navi10, by default the below four features are enabled.
gfxclk deep sleep: enabled and verified
fw dstate: enabled and then soc ulv is verified
dcefclk deep sleep: enabled and verified. notice that on different boards,
due to the minimum dcefclk deep sleep setting in VBIOS, we may not see dcefclk
deep sleep kicking in.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Kenneth Feng
2019-05-14 17:08:36 +08:00
committed by Alex Deucher
parent c0b9d6d2f1
commit 3a3c51dd90
1 changed files with 4 additions and 1 deletions
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5
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
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@@ -326,7 +326,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
| FEATURE_MASK(FEATURE_MMHUB_PG_BIT)
| FEATURE_MASK(FEATURE_ATHUB_PG_BIT)
| FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
| FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
| FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)