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arm64: dts: renesas: salvator-common: Describe PCIe/USB3.0 clock generator
Describe the 9FGV0841 PCIe and USB3.0 clock generator present on both Salvator-X and Salvator-XS boards. The clock generator supplies 100 MHz differential clock for both PCIe ports, as well as for the USB 3.0 PHY. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260118135038.8033-8-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
committed by
Geert Uytterhoeven
parent
c6ffd32627
commit
39ef5f2dac
@@ -75,6 +75,12 @@ backlight: backlight {
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enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
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};
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pcie_usb_refclk: clk-x7 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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cvbs-in {
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compatible = "composite-video-connector";
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label = "CVBS IN";
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@@ -523,6 +529,13 @@ pca9654: gpio@20 {
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#gpio-cells = <2>;
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};
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pcie_usb_clk: clk@68 {
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compatible = "renesas,9fgv0841";
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reg = <0x68>;
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clocks = <&pcie_usb_refclk>;
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#clock-cells = <1>;
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};
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video-receiver@70 {
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compatible = "adi,adv7482";
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reg = <0x70 0x71 0x72 0x73 0x74 0x75
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@@ -640,17 +653,27 @@ &ohci1 {
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};
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&pcie_bus_clk {
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clock-frequency = <100000000>;
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status = "disabled";
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};
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&pciec0 {
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clocks = <&cpg CPG_MOD 319>, <&pcie_usb_clk 1>;
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status = "okay";
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};
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&pciec0_rp {
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clocks = <&pcie_usb_clk 3>;
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};
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&pciec1 {
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clocks = <&cpg CPG_MOD 318>, <&pcie_usb_clk 2>;
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status = "okay";
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};
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&pciec1_rp {
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clocks = <&pcie_usb_clk 4>;
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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@@ -1038,11 +1061,12 @@ &usb3_peri0 {
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};
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&usb3_phy0 {
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clocks = <&cpg CPG_MOD 328>, <&pcie_usb_clk 6>, <&usb_extal_clk>;
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status = "okay";
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};
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&usb3s0_clk {
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clock-frequency = <100000000>;
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status = "disabled";
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};
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&vin0 {
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