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drm/amd/display: Fix DP LT sequence on EQ fail

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[Why]
The number of lanes wasn't being reset to maximum when reducing link
rate due to an EQ failure. This could result in having fewer lanes in
the verified link capabilities, a lower maximum link bandwidth, and
fewer modes being supported.

[How]
Reset the number of lanes to max when dropping link rate due to EQ
failure during link training.

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Ilya <Ilya.Bakoulin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ilya
2022-01-27 14:14:32 -05:00
committed by Alex Deucher
parent 559e265522
commit 39da460fd4
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
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@@ -3504,6 +3504,7 @@ static bool decide_fallback_link_setting(
current_link_setting->link_rate =
reduce_link_rate(
current_link_setting->link_rate);
current_link_setting->lane_count = initial_link_settings.lane_count;
} else {
return false;
}
@@ -3516,6 +3517,7 @@ static bool decide_fallback_link_setting(
current_link_setting->link_rate =
reduce_link_rate(
current_link_setting->link_rate);
current_link_setting->lane_count = initial_link_settings.lane_count;
} else {
return false;
}