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drm/amd/display: increase bb clock for DCN351

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[Why and how]

Bounding box clocks for DCN351 should be increased as per request

Reviewed-by: Swapnil Patel <swapnil.patel@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Xi Liu <xi.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xi Liu
2024-03-07 11:51:56 -05:00
committed by Alex Deucher
parent f2afc8d4c3
commit 398a16e1f0
1 changed files with 76 additions and 14 deletions
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90
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
View File

@@ -98,51 +98,110 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_51_soc = {
.clock_limits = {
{
.state = 0,
.dispclk_mhz = 1200.0,
.dppclk_mhz = 1200.0,
.dcfclk_mhz = 400.0,
.fabricclk_mhz = 400.0,
.socclk_mhz = 600.0,
.dram_speed_mts = 3200.0,
.dispclk_mhz = 600.0,
.dppclk_mhz = 600.0,
.phyclk_mhz = 600.0,
.phyclk_d18_mhz = 667.0,
.dscclk_mhz = 186.0,
.dscclk_mhz = 200.0,
.dtbclk_mhz = 600.0,
},
{
.state = 1,
.dispclk_mhz = 1200.0,
.dppclk_mhz = 1200.0,
.dcfclk_mhz = 600.0,
.fabricclk_mhz = 1000.0,
.socclk_mhz = 733.0,
.dram_speed_mts = 6400.0,
.dispclk_mhz = 800.0,
.dppclk_mhz = 800.0,
.phyclk_mhz = 810.0,
.phyclk_d18_mhz = 667.0,
.dscclk_mhz = 209.0,
.dscclk_mhz = 266.7,
.dtbclk_mhz = 600.0,
},
{
.state = 2,
.dispclk_mhz = 1200.0,
.dppclk_mhz = 1200.0,
.dcfclk_mhz = 738.0,
.fabricclk_mhz = 1200.0,
.socclk_mhz = 880.0,
.dram_speed_mts = 7500.0,
.dispclk_mhz = 800.0,
.dppclk_mhz = 800.0,
.phyclk_mhz = 810.0,
.phyclk_d18_mhz = 667.0,
.dscclk_mhz = 209.0,
.dscclk_mhz = 266.7,
.dtbclk_mhz = 600.0,
},
{
.state = 3,
.dispclk_mhz = 1200.0,
.dppclk_mhz = 1200.0,
.dcfclk_mhz = 800.0,
.fabricclk_mhz = 1400.0,
.socclk_mhz = 978.0,
.dram_speed_mts = 7500.0,
.dispclk_mhz = 960.0,
.dppclk_mhz = 960.0,
.phyclk_mhz = 810.0,
.phyclk_d18_mhz = 667.0,
.dscclk_mhz = 371.0,
.dscclk_mhz = 320.0,
.dtbclk_mhz = 600.0,
},
{
.state = 4,
.dcfclk_mhz = 873.0,
.fabricclk_mhz = 1600.0,
.socclk_mhz = 1100.0,
.dram_speed_mts = 8533.0,
.dispclk_mhz = 1066.7,
.dppclk_mhz = 1066.7,
.phyclk_mhz = 810.0,
.phyclk_d18_mhz = 667.0,
.dscclk_mhz = 355.6,
.dtbclk_mhz = 600.0,
},
{
.state = 5,
.dcfclk_mhz = 960.0,
.fabricclk_mhz = 1700.0,
.socclk_mhz = 1257.0,
.dram_speed_mts = 8533.0,
.dispclk_mhz = 1200.0,
.dppclk_mhz = 1200.0,
.phyclk_mhz = 810.0,
.phyclk_d18_mhz = 667.0,
.dscclk_mhz = 417.0,
.dscclk_mhz = 400.0,
.dtbclk_mhz = 600.0,
},
{
.state = 6,
.dcfclk_mhz = 1067.0,
.fabricclk_mhz = 1850.0,
.socclk_mhz = 1257.0,
.dram_speed_mts = 8533.0,
.dispclk_mhz = 1371.4,
.dppclk_mhz = 1371.4,
.phyclk_mhz = 810.0,
.phyclk_d18_mhz = 667.0,
.dscclk_mhz = 457.1,
.dtbclk_mhz = 600.0,
},
{
.state = 7,
.dcfclk_mhz = 1200.0,
.fabricclk_mhz = 2000.0,
.socclk_mhz = 1467.0,
.dram_speed_mts = 8533.0,
.dispclk_mhz = 1600.0,
.dppclk_mhz = 1600.0,
.phyclk_mhz = 810.0,
.phyclk_d18_mhz = 667.0,
.dscclk_mhz = 533.3,
.dtbclk_mhz = 600.0,
},
},
.num_states = 5,
.num_states = 8,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.sr_exit_z8_time_us = 250.0,
@@ -177,6 +236,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_51_soc = {
.do_urgent_latency_adjustment = 0,
.urgent_latency_adjustment_fabric_clock_component_us = 0,
.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
.num_chans = 4,
.dram_clock_change_latency_us = 11.72,
.dispclk_dppclk_vco_speed_mhz = 2400.0,
};
/*