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Merge patch series "pinctrl: intel: Consolidate struct intel_padgroup initialisers"

Browse Source 
Andy Shevchenko <andriy.shevchenko@linux.intel.com> says:

We have plenty of repetitive *_GPP() macros across the drivers.
Consolidate them under a newly introduced INTEL_GPP().

Link: https://patch.msgid.link/20251104145814.1018867-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This commit is contained in:
Andy Shevchenko
2025-11-05 18:15:07 +01:00
parent ce27278119 d99b7a9d51
commit 396f45a34e
10 changed files with 199 additions and 262 deletions
Download Patch File Download Diff File Expand all files Collapse all files

68
drivers/pinctrl/intel/pinctrl-alderlake.c
View File

@@ -27,14 +27,6 @@
#define ADL_S_GPI_IS 0x200
#define ADL_S_GPI_IE 0x220
#define ADL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define ADL_N_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_N)
@@ -316,28 +308,28 @@ static const struct pinctrl_pin_desc adln_pins[] = {
};
static const struct intel_padgroup adln_community0_gpps[] = {
ADL_GPP(0, 0, 25, 0), /* GPP_B */
ADL_GPP(1, 26, 41, 32), /* GPP_T */
ADL_GPP(2, 42, 66, 64), /* GPP_A */
INTEL_GPP(0, 0, 25, 0), /* GPP_B */
INTEL_GPP(1, 26, 41, 32), /* GPP_T */
INTEL_GPP(2, 42, 66, 64), /* GPP_A */
};
static const struct intel_padgroup adln_community1_gpps[] = {
ADL_GPP(0, 67, 74, 96), /* GPP_S */
ADL_GPP(1, 75, 94, 128), /* GPP_I */
ADL_GPP(2, 95, 118, 160), /* GPP_H */
ADL_GPP(3, 119, 139, 192), /* GPP_D */
ADL_GPP(4, 140, 168, 224), /* vGPIO */
INTEL_GPP(0, 67, 74, 96), /* GPP_S */
INTEL_GPP(1, 75, 94, 128), /* GPP_I */
INTEL_GPP(2, 95, 118, 160), /* GPP_H */
INTEL_GPP(3, 119, 139, 192), /* GPP_D */
INTEL_GPP(4, 140, 168, 224), /* vGPIO */
};
static const struct intel_padgroup adln_community4_gpps[] = {
ADL_GPP(0, 169, 192, 256), /* GPP_C */
ADL_GPP(1, 193, 217, 288), /* GPP_F */
ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
ADL_GPP(3, 224, 248, 320), /* GPP_E */
INTEL_GPP(0, 169, 192, 256), /* GPP_C */
INTEL_GPP(1, 193, 217, 288), /* GPP_F */
INTEL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
INTEL_GPP(3, 224, 248, 320), /* GPP_E */
};
static const struct intel_padgroup adln_community5_gpps[] = {
ADL_GPP(0, 249, 256, 352), /* GPP_R */
INTEL_GPP(0, 249, 256, 352), /* GPP_R */
};
static const struct intel_community adln_communities[] = {
@@ -680,35 +672,35 @@ static const struct pinctrl_pin_desc adls_pins[] = {
};
static const struct intel_padgroup adls_community0_gpps[] = {
ADL_GPP(0, 0, 24, 0), /* GPP_I */
ADL_GPP(1, 25, 47, 32), /* GPP_R */
ADL_GPP(2, 48, 59, 64), /* GPP_J */
ADL_GPP(3, 60, 86, 96), /* vGPIO */
ADL_GPP(4, 87, 94, 128), /* vGPIO_0 */
INTEL_GPP(0, 0, 24, 0), /* GPP_I */
INTEL_GPP(1, 25, 47, 32), /* GPP_R */
INTEL_GPP(2, 48, 59, 64), /* GPP_J */
INTEL_GPP(3, 60, 86, 96), /* vGPIO */
INTEL_GPP(4, 87, 94, 128), /* vGPIO_0 */
};
static const struct intel_padgroup adls_community1_gpps[] = {
ADL_GPP(0, 95, 118, 160), /* GPP_B */
ADL_GPP(1, 119, 126, 192), /* GPP_G */
ADL_GPP(2, 127, 150, 224), /* GPP_H */
INTEL_GPP(0, 95, 118, 160), /* GPP_B */
INTEL_GPP(1, 119, 126, 192), /* GPP_G */
INTEL_GPP(2, 127, 150, 224), /* GPP_H */
};
static const struct intel_padgroup adls_community3_gpps[] = {
ADL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */
ADL_GPP(1, 160, 175, 256), /* GPP_A */
ADL_GPP(2, 176, 199, 288), /* GPP_C */
INTEL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */
INTEL_GPP(1, 160, 175, 256), /* GPP_A */
INTEL_GPP(2, 176, 199, 288), /* GPP_C */
};
static const struct intel_padgroup adls_community4_gpps[] = {
ADL_GPP(0, 200, 207, 320), /* GPP_S */
ADL_GPP(1, 208, 230, 352), /* GPP_E */
ADL_GPP(2, 231, 245, 384), /* GPP_K */
ADL_GPP(3, 246, 269, 416), /* GPP_F */
INTEL_GPP(0, 200, 207, 320), /* GPP_S */
INTEL_GPP(1, 208, 230, 352), /* GPP_E */
INTEL_GPP(2, 231, 245, 384), /* GPP_K */
INTEL_GPP(3, 246, 269, 416), /* GPP_F */
};
static const struct intel_padgroup adls_community5_gpps[] = {
ADL_GPP(0, 270, 294, 448), /* GPP_D */
ADL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */
INTEL_GPP(0, 270, 294, 448), /* GPP_D */
INTEL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */
};
static const struct intel_community adls_communities[] = {

68
drivers/pinctrl/intel/pinctrl-cannonlake.c
View File

@@ -28,14 +28,6 @@
#define CNL_H_GPI_IS 0x100
#define CNL_H_GPI_IE 0x120
#define CNL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define CNL_LP_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP)
@@ -362,32 +354,32 @@ static const struct pinctrl_pin_desc cnlh_pins[] = {
};
static const struct intel_padgroup cnlh_community0_gpps[] = {
CNL_GPP(0, 0, 24, 0), /* GPP_A */
CNL_GPP(1, 25, 50, 32), /* GPP_B */
INTEL_GPP(0, 0, 24, 0), /* GPP_A */
INTEL_GPP(1, 25, 50, 32), /* GPP_B */
};
static const struct intel_padgroup cnlh_community1_gpps[] = {
CNL_GPP(0, 51, 74, 64), /* GPP_C */
CNL_GPP(1, 75, 98, 96), /* GPP_D */
CNL_GPP(2, 99, 106, 128), /* GPP_G */
CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */
CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
INTEL_GPP(0, 51, 74, 64), /* GPP_C */
INTEL_GPP(1, 75, 98, 96), /* GPP_D */
INTEL_GPP(2, 99, 106, 128), /* GPP_G */
INTEL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
INTEL_GPP(4, 115, 146, 160), /* vGPIO_0 */
INTEL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
};
static const struct intel_padgroup cnlh_community3_gpps[] = {
CNL_GPP(0, 155, 178, 192), /* GPP_K */
CNL_GPP(1, 179, 202, 224), /* GPP_H */
CNL_GPP(2, 203, 215, 256), /* GPP_E */
CNL_GPP(3, 216, 239, 288), /* GPP_F */
CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
INTEL_GPP(0, 155, 178, 192), /* GPP_K */
INTEL_GPP(1, 179, 202, 224), /* GPP_H */
INTEL_GPP(2, 203, 215, 256), /* GPP_E */
INTEL_GPP(3, 216, 239, 288), /* GPP_F */
INTEL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
};
static const struct intel_padgroup cnlh_community4_gpps[] = {
CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
CNL_GPP(2, 269, 286, 320), /* GPP_I */
CNL_GPP(3, 287, 298, 352), /* GPP_J */
INTEL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
INTEL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
INTEL_GPP(2, 269, 286, 320), /* GPP_I */
INTEL_GPP(3, 287, 298, 352), /* GPP_J */
};
static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
@@ -780,25 +772,25 @@ static const struct intel_function cnllp_functions[] = {
};
static const struct intel_padgroup cnllp_community0_gpps[] = {
CNL_GPP(0, 0, 24, 0), /* GPP_A */
CNL_GPP(1, 25, 50, 32), /* GPP_B */
CNL_GPP(2, 51, 58, 64), /* GPP_G */
CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
INTEL_GPP(0, 0, 24, 0), /* GPP_A */
INTEL_GPP(1, 25, 50, 32), /* GPP_B */
INTEL_GPP(2, 51, 58, 64), /* GPP_G */
INTEL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
};
static const struct intel_padgroup cnllp_community1_gpps[] = {
CNL_GPP(0, 68, 92, 96), /* GPP_D */
CNL_GPP(1, 93, 116, 128), /* GPP_F */
CNL_GPP(2, 117, 140, 160), /* GPP_H */
CNL_GPP(3, 141, 172, 192), /* vGPIO */
CNL_GPP(4, 173, 180, 224), /* vGPIO */
INTEL_GPP(0, 68, 92, 96), /* GPP_D */
INTEL_GPP(1, 93, 116, 128), /* GPP_F */
INTEL_GPP(2, 117, 140, 160), /* GPP_H */
INTEL_GPP(3, 141, 172, 192), /* vGPIO */
INTEL_GPP(4, 173, 180, 224), /* vGPIO */
};
static const struct intel_padgroup cnllp_community4_gpps[] = {
CNL_GPP(0, 181, 204, 256), /* GPP_C */
CNL_GPP(1, 205, 228, 288), /* GPP_E */
CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
INTEL_GPP(0, 181, 204, 256), /* GPP_C */
INTEL_GPP(1, 205, 228, 288), /* GPP_E */
INTEL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
INTEL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
};
static const struct intel_community cnllp_communities[] = {

60
drivers/pinctrl/intel/pinctrl-icelake.c
View File

@@ -28,14 +28,6 @@
#define ICL_N_GPI_IS 0x100
#define ICL_N_GPI_IE 0x120
#define ICL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define ICL_LP_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_LP)
@@ -302,29 +294,29 @@ static const struct pinctrl_pin_desc icllp_pins[] = {
};
static const struct intel_padgroup icllp_community0_gpps[] = {
ICL_GPP(0, 0, 7, 0), /* GPP_G */
ICL_GPP(1, 8, 33, 32), /* GPP_B */
ICL_GPP(2, 34, 58, 64), /* GPP_A */
INTEL_GPP(0, 0, 7, 0), /* GPP_G */
INTEL_GPP(1, 8, 33, 32), /* GPP_B */
INTEL_GPP(2, 34, 58, 64), /* GPP_A */
};
static const struct intel_padgroup icllp_community1_gpps[] = {
ICL_GPP(0, 59, 82, 96), /* GPP_H */
ICL_GPP(1, 83, 103, 128), /* GPP_D */
ICL_GPP(2, 104, 123, 160), /* GPP_F */
ICL_GPP(3, 124, 152, 192), /* vGPIO */
INTEL_GPP(0, 59, 82, 96), /* GPP_H */
INTEL_GPP(1, 83, 103, 128), /* GPP_D */
INTEL_GPP(2, 104, 123, 160), /* GPP_F */
INTEL_GPP(3, 124, 152, 192), /* vGPIO */
};
static const struct intel_padgroup icllp_community4_gpps[] = {
ICL_GPP(0, 153, 176, 224), /* GPP_C */
ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
ICL_GPP(2, 183, 206, 256), /* GPP_E */
ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */
INTEL_GPP(0, 153, 176, 224), /* GPP_C */
INTEL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
INTEL_GPP(2, 183, 206, 256), /* GPP_E */
INTEL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */
};
static const struct intel_padgroup icllp_community5_gpps[] = {
ICL_GPP(0, 216, 223, 288), /* GPP_R */
ICL_GPP(1, 224, 231, 320), /* GPP_S */
ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */
INTEL_GPP(0, 216, 223, 288), /* GPP_R */
INTEL_GPP(1, 224, 231, 320), /* GPP_S */
INTEL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */
};
static const struct intel_community icllp_communities[] = {
@@ -632,27 +624,27 @@ static const struct pinctrl_pin_desc icln_pins[] = {
};
static const struct intel_padgroup icln_community0_gpps[] = {
ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */
ICL_GPP(1, 9, 34, 32), /* GPP_B */
ICL_GPP(2, 35, 55, 64), /* GPP_A */
ICL_GPP(3, 56, 63, 96), /* GPP_S */
ICL_GPP(4, 64, 71, 128), /* GPP_R */
INTEL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */
INTEL_GPP(1, 9, 34, 32), /* GPP_B */
INTEL_GPP(2, 35, 55, 64), /* GPP_A */
INTEL_GPP(3, 56, 63, 96), /* GPP_S */
INTEL_GPP(4, 64, 71, 128), /* GPP_R */
};
static const struct intel_padgroup icln_community1_gpps[] = {
ICL_GPP(0, 72, 95, 160), /* GPP_H */
ICL_GPP(1, 96, 121, 192), /* GPP_D */
ICL_GPP(2, 122, 150, 224), /* vGPIO */
ICL_GPP(3, 151, 174, 256), /* GPP_C */
INTEL_GPP(0, 72, 95, 160), /* GPP_H */
INTEL_GPP(1, 96, 121, 192), /* GPP_D */
INTEL_GPP(2, 122, 150, 224), /* vGPIO */
INTEL_GPP(3, 151, 174, 256), /* GPP_C */
};
static const struct intel_padgroup icln_community4_gpps[] = {
ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
ICL_GPP(1, 181, 204, 288), /* GPP_E */
INTEL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
INTEL_GPP(1, 181, 204, 288), /* GPP_E */
};
static const struct intel_padgroup icln_community5_gpps[] = {
ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */
INTEL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */
};
static const struct intel_community icln_communities[] = {

9
drivers/pinctrl/intel/pinctrl-intel.h
View File

@@ -76,6 +76,15 @@ enum {
INTEL_GPIO_BASE_MATCH = 0,
};
/* Initialise struct intel_padgroup */
#define INTEL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
/**
* struct intel_community - Intel pin community description
* @barno: MMIO BAR number where registers for this community reside

34
drivers/pinctrl/intel/pinctrl-jasperlake.c
View File

@@ -21,14 +21,6 @@
#define JSL_GPI_IS 0x100
#define JSL_GPI_IE 0x120
#define JSL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define JSL_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, JSL)
@@ -283,28 +275,28 @@ static const struct pinctrl_pin_desc jsl_pins[] = {
};
static const struct intel_padgroup jsl_community0_gpps[] = {
JSL_GPP(0, 0, 19, 320), /* GPP_F */
JSL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP), /* SPI */
JSL_GPP(2, 29, 54, 32), /* GPP_B */
JSL_GPP(3, 55, 75, 64), /* GPP_A */
JSL_GPP(4, 76, 83, 96), /* GPP_S */
JSL_GPP(5, 84, 91, 128), /* GPP_R */
INTEL_GPP(0, 0, 19, 320), /* GPP_F */
INTEL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP), /* SPI */
INTEL_GPP(2, 29, 54, 32), /* GPP_B */
INTEL_GPP(3, 55, 75, 64), /* GPP_A */
INTEL_GPP(4, 76, 83, 96), /* GPP_S */
INTEL_GPP(5, 84, 91, 128), /* GPP_R */
};
static const struct intel_padgroup jsl_community1_gpps[] = {
JSL_GPP(0, 92, 115, 160), /* GPP_H */
JSL_GPP(1, 116, 141, 192), /* GPP_D */
JSL_GPP(2, 142, 170, 224), /* vGPIO */
JSL_GPP(3, 171, 194, 256), /* GPP_C */
INTEL_GPP(0, 92, 115, 160), /* GPP_H */
INTEL_GPP(1, 116, 141, 192), /* GPP_D */
INTEL_GPP(2, 142, 170, 224), /* vGPIO */
INTEL_GPP(3, 171, 194, 256), /* GPP_C */
};
static const struct intel_padgroup jsl_community4_gpps[] = {
JSL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
JSL_GPP(1, 201, 224, 288), /* GPP_E */
INTEL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
INTEL_GPP(1, 201, 224, 288), /* GPP_E */
};
static const struct intel_padgroup jsl_community5_gpps[] = {
JSL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO), /* GPP_G */
INTEL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO), /* GPP_G */
};
static const struct intel_community jsl_communities[] = {

26
drivers/pinctrl/intel/pinctrl-lakefield.c
View File

@@ -21,14 +21,6 @@
#define LKF_GPI_IS 0x100
#define LKF_GPI_IE 0x110
#define LKF_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define LKF_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, LKF)
@@ -308,24 +300,24 @@ static const struct pinctrl_pin_desc lkf_pins[] = {
};
static const struct intel_padgroup lkf_community0_gpps[] = {
LKF_GPP(0, 0, 31, 0), /* EAST_0 */
LKF_GPP(1, 32, 59, 32), /* EAST_1 */
INTEL_GPP(0, 0, 31, 0), /* EAST_0 */
INTEL_GPP(1, 32, 59, 32), /* EAST_1 */
};
static const struct intel_padgroup lkf_community1_gpps[] = {
LKF_GPP(0, 60, 91, 64), /* NORTHWEST_0 */
LKF_GPP(1, 92, 123, 96), /* NORTHWEST_1 */
LKF_GPP(2, 124, 148, 128), /* NORTHWEST_2 */
INTEL_GPP(0, 60, 91, 64), /* NORTHWEST_0 */
INTEL_GPP(1, 92, 123, 96), /* NORTHWEST_1 */
INTEL_GPP(2, 124, 148, 128), /* NORTHWEST_2 */
};
static const struct intel_padgroup lkf_community2_gpps[] = {
LKF_GPP(0, 149, 180, 160), /* WEST_0 */
LKF_GPP(1, 181, 212, 192), /* WEST_1 */
LKF_GPP(2, 213, 237, 224), /* WEST_2 */
INTEL_GPP(0, 149, 180, 160), /* WEST_0 */
INTEL_GPP(1, 181, 212, 192), /* WEST_1 */
INTEL_GPP(2, 213, 237, 224), /* WEST_2 */
};
static const struct intel_padgroup lkf_community3_gpps[] = {
LKF_GPP(0, 238, 266, 256), /* SOUTHEAST */
INTEL_GPP(0, 238, 266, 256), /* SOUTHEAST */
};
static const struct intel_community lkf_communities[] = {

54
drivers/pinctrl/intel/pinctrl-meteorlake.c
View File

@@ -27,14 +27,6 @@
#define MTL_S_GPI_IS 0x200
#define MTL_S_GPI_IE 0x210
#define MTL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define MTL_P_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_P)
@@ -349,33 +341,33 @@ static const struct pinctrl_pin_desc mtlp_pins[] = {
};
static const struct intel_padgroup mtlp_community0_gpps[] = {
MTL_GPP(0, 0, 4, 0), /* CPU */
MTL_GPP(1, 5, 28, 32), /* GPP_V */
MTL_GPP(2, 29, 52, 64), /* GPP_C */
INTEL_GPP(0, 0, 4, 0), /* CPU */
INTEL_GPP(1, 5, 28, 32), /* GPP_V */
INTEL_GPP(2, 29, 52, 64), /* GPP_C */
};
static const struct intel_padgroup mtlp_community1_gpps[] = {
MTL_GPP(0, 53, 77, 96), /* GPP_A */
MTL_GPP(1, 78, 102, 128), /* GPP_E */
INTEL_GPP(0, 53, 77, 96), /* GPP_A */
INTEL_GPP(1, 78, 102, 128), /* GPP_E */
};
static const struct intel_padgroup mtlp_community3_gpps[] = {
MTL_GPP(0, 103, 128, 160), /* GPP_H */
MTL_GPP(1, 129, 154, 192), /* GPP_F */
MTL_GPP(2, 155, 169, 224), /* SPI0 */
MTL_GPP(3, 170, 183, 256), /* vGPIO_3 */
INTEL_GPP(0, 103, 128, 160), /* GPP_H */
INTEL_GPP(1, 129, 154, 192), /* GPP_F */
INTEL_GPP(2, 155, 169, 224), /* SPI0 */
INTEL_GPP(3, 170, 183, 256), /* vGPIO_3 */
};
static const struct intel_padgroup mtlp_community4_gpps[] = {
MTL_GPP(0, 184, 191, 288), /* GPP_S */
MTL_GPP(1, 192, 203, 320), /* JTAG */
INTEL_GPP(0, 184, 191, 288), /* GPP_S */
INTEL_GPP(1, 192, 203, 320), /* JTAG */
};
static const struct intel_padgroup mtlp_community5_gpps[] = {
MTL_GPP(0, 204, 228, 352), /* GPP_B */
MTL_GPP(1, 229, 253, 384), /* GPP_D */
MTL_GPP(2, 254, 285, 416), /* vGPIO_0 */
MTL_GPP(3, 286, 288, 448), /* vGPIO_1 */
INTEL_GPP(0, 204, 228, 352), /* GPP_B */
INTEL_GPP(1, 229, 253, 384), /* GPP_D */
INTEL_GPP(2, 254, 285, 416), /* vGPIO_0 */
INTEL_GPP(3, 286, 288, 448), /* vGPIO_1 */
};
static const struct intel_community mtlp_communities[] = {
@@ -554,20 +546,20 @@ static const struct pinctrl_pin_desc mtls_pins[] = {
};
static const struct intel_padgroup mtls_community0_gpps[] = {
MTL_GPP(0, 0, 27, 0), /* GPP_A */
MTL_GPP(1, 28, 46, 32), /* vGPIO_0 */
MTL_GPP(2, 47, 73, 64), /* GPP_C */
INTEL_GPP(0, 0, 27, 0), /* GPP_A */
INTEL_GPP(1, 28, 46, 32), /* vGPIO_0 */
INTEL_GPP(2, 47, 73, 64), /* GPP_C */
};
static const struct intel_padgroup mtls_community1_gpps[] = {
MTL_GPP(0, 74, 93, 96), /* GPP_B */
MTL_GPP(1, 94, 95, 128), /* vGPIO_3 */
MTL_GPP(2, 96, 119, 160), /* GPP_D */
INTEL_GPP(0, 74, 93, 96), /* GPP_B */
INTEL_GPP(1, 94, 95, 128), /* vGPIO_3 */
INTEL_GPP(2, 96, 119, 160), /* GPP_D */
};
static const struct intel_padgroup mtls_community3_gpps[] = {
MTL_GPP(0, 120, 135, 192), /* JTAG_CPU */
MTL_GPP(1, 136, 147, 224), /* vGPIO_4 */
INTEL_GPP(0, 120, 135, 192), /* JTAG_CPU */
INTEL_GPP(1, 136, 147, 224), /* vGPIO_4 */
};
static const struct intel_community mtls_communities[] = {

46
drivers/pinctrl/intel/pinctrl-meteorpoint.c
View File

@@ -21,14 +21,6 @@
#define MTP_GPI_IS 0x200
#define MTP_GPI_IE 0x220
#define MTP_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define MTP_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, MTP)
@@ -395,37 +387,37 @@ static const struct pinctrl_pin_desc mtps_pins[] = {
};
static const struct intel_padgroup mtps_community0_gpps[] = {
MTP_GPP(0, 0, 24, 0), /* GPP_D */
MTP_GPP(1, 25, 38, 32), /* GPP_R */
MTP_GPP(2, 39, 56, 64), /* GPP_J */
MTP_GPP(3, 57, 87, 96), /* vGPIO */
INTEL_GPP(0, 0, 24, 0), /* GPP_D */
INTEL_GPP(1, 25, 38, 32), /* GPP_R */
INTEL_GPP(2, 39, 56, 64), /* GPP_J */
INTEL_GPP(3, 57, 87, 96), /* vGPIO */
};
static const struct intel_padgroup mtps_community1_gpps[] = {
MTP_GPP(0, 88, 102, 128), /* GPP_A */
MTP_GPP(1, 103, 114, 160), /* DIR_ESPI */
MTP_GPP(2, 115, 136, 192), /* GPP_B */
INTEL_GPP(0, 88, 102, 128), /* GPP_A */
INTEL_GPP(1, 103, 114, 160), /* DIR_ESPI */
INTEL_GPP(2, 115, 136, 192), /* GPP_B */
};
static const struct intel_padgroup mtps_community3_gpps[] = {
MTP_GPP(0, 137, 145, 224), /* SPI0 */
MTP_GPP(1, 146, 169, 256), /* GPP_C */
MTP_GPP(2, 170, 189, 288), /* GPP_H */
MTP_GPP(3, 190, 193, 320), /* vGPIO_3 */
MTP_GPP(4, 194, 201, 352), /* vGPIO_0 */
MTP_GPP(5, 202, 232, 384), /* vGPIO_4 */
INTEL_GPP(0, 137, 145, 224), /* SPI0 */
INTEL_GPP(1, 146, 169, 256), /* GPP_C */
INTEL_GPP(2, 170, 189, 288), /* GPP_H */
INTEL_GPP(3, 190, 193, 320), /* vGPIO_3 */
INTEL_GPP(4, 194, 201, 352), /* vGPIO_0 */
INTEL_GPP(5, 202, 232, 384), /* vGPIO_4 */
};
static const struct intel_padgroup mtps_community4_gpps[] = {
MTP_GPP(0, 233, 240, 416), /* GPP_S */
MTP_GPP(1, 241, 263, 448), /* GPP_E */
MTP_GPP(2, 264, 277, 480), /* GPP_K */
MTP_GPP(3, 278, 301, 512), /* GPP_F */
INTEL_GPP(0, 233, 240, 416), /* GPP_S */
INTEL_GPP(1, 241, 263, 448), /* GPP_E */
INTEL_GPP(2, 264, 277, 480), /* GPP_K */
INTEL_GPP(3, 278, 301, 512), /* GPP_F */
};
static const struct intel_padgroup mtps_community5_gpps[] = {
MTP_GPP(0, 302, 322, 544), /* GPP_I */
MTP_GPP(1, 323, 338, 576), /* JTAG_CPU */
INTEL_GPP(0, 302, 322, 544), /* GPP_I */
INTEL_GPP(1, 323, 338, 576), /* JTAG_CPU */
};
static const struct intel_community mtps_communities[] = {

26
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
View File

@@ -28,14 +28,6 @@
#define SPT_LP_GPI_IS 0x100
#define SPT_LP_GPI_IE 0x120
#define SPT_H_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define SPT_H_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, SPT_H)
@@ -538,21 +530,21 @@ static const struct intel_function spth_functions[] = {
};
static const struct intel_padgroup spth_community0_gpps[] = {
SPT_H_GPP(0, 0, 23, 0), /* GPP_A */
SPT_H_GPP(1, 24, 47, 24), /* GPP_B */
INTEL_GPP(0, 0, 23, 0), /* GPP_A */
INTEL_GPP(1, 24, 47, 24), /* GPP_B */
};
static const struct intel_padgroup spth_community1_gpps[] = {
SPT_H_GPP(0, 48, 71, 48), /* GPP_C */
SPT_H_GPP(1, 72, 95, 72), /* GPP_D */
SPT_H_GPP(2, 96, 108, 96), /* GPP_E */
SPT_H_GPP(3, 109, 132, 120), /* GPP_F */
SPT_H_GPP(4, 133, 156, 144), /* GPP_G */
SPT_H_GPP(5, 157, 180, 168), /* GPP_H */
INTEL_GPP(0, 48, 71, 48), /* GPP_C */
INTEL_GPP(1, 72, 95, 72), /* GPP_D */
INTEL_GPP(2, 96, 108, 96), /* GPP_E */
INTEL_GPP(3, 109, 132, 120), /* GPP_F */
INTEL_GPP(4, 133, 156, 144), /* GPP_G */
INTEL_GPP(5, 157, 180, 168), /* GPP_H */
};
static const struct intel_padgroup spth_community3_gpps[] = {
SPT_H_GPP(0, 181, 191, 192), /* GPP_I */
INTEL_GPP(0, 181, 191, 192), /* GPP_I */
};
static const struct intel_community spth_communities[] = {

70
drivers/pinctrl/intel/pinctrl-tigerlake.c
View File

@@ -28,14 +28,6 @@
#define TGL_H_GPI_IS 0x100
#define TGL_H_GPI_IE 0x120
#define TGL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define TGL_LP_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_LP)
@@ -339,30 +331,30 @@ static const struct pinctrl_pin_desc tgllp_pins[] = {
};
static const struct intel_padgroup tgllp_community0_gpps[] = {
TGL_GPP(0, 0, 25, 0), /* GPP_B */
TGL_GPP(1, 26, 41, 32), /* GPP_T */
TGL_GPP(2, 42, 66, 64), /* GPP_A */
INTEL_GPP(0, 0, 25, 0), /* GPP_B */
INTEL_GPP(1, 26, 41, 32), /* GPP_T */
INTEL_GPP(2, 42, 66, 64), /* GPP_A */
};
static const struct intel_padgroup tgllp_community1_gpps[] = {
TGL_GPP(0, 67, 74, 96), /* GPP_S */
TGL_GPP(1, 75, 98, 128), /* GPP_H */
TGL_GPP(2, 99, 119, 160), /* GPP_D */
TGL_GPP(3, 120, 143, 192), /* GPP_U */
TGL_GPP(4, 144, 170, 224), /* vGPIO */
INTEL_GPP(0, 67, 74, 96), /* GPP_S */
INTEL_GPP(1, 75, 98, 128), /* GPP_H */
INTEL_GPP(2, 99, 119, 160), /* GPP_D */
INTEL_GPP(3, 120, 143, 192), /* GPP_U */
INTEL_GPP(4, 144, 170, 224), /* vGPIO */
};
static const struct intel_padgroup tgllp_community4_gpps[] = {
TGL_GPP(0, 171, 194, 256), /* GPP_C */
TGL_GPP(1, 195, 219, 288), /* GPP_F */
TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
TGL_GPP(3, 226, 250, 320), /* GPP_E */
TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */
INTEL_GPP(0, 171, 194, 256), /* GPP_C */
INTEL_GPP(1, 195, 219, 288), /* GPP_F */
INTEL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
INTEL_GPP(3, 226, 250, 320), /* GPP_E */
INTEL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */
};
static const struct intel_padgroup tgllp_community5_gpps[] = {
TGL_GPP(0, 260, 267, 352), /* GPP_R */
TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */
INTEL_GPP(0, 260, 267, 352), /* GPP_R */
INTEL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */
};
static const struct intel_community tgllp_communities[] = {
@@ -691,34 +683,34 @@ static const struct pinctrl_pin_desc tglh_pins[] = {
};
static const struct intel_padgroup tglh_community0_gpps[] = {
TGL_GPP(0, 0, 24, 0), /* GPP_A */
TGL_GPP(1, 25, 44, 32), /* GPP_R */
TGL_GPP(2, 45, 70, 64), /* GPP_B */
TGL_GPP(3, 71, 78, 96), /* vGPIO_0 */
INTEL_GPP(0, 0, 24, 0), /* GPP_A */
INTEL_GPP(1, 25, 44, 32), /* GPP_R */
INTEL_GPP(2, 45, 70, 64), /* GPP_B */
INTEL_GPP(3, 71, 78, 96), /* vGPIO_0 */
};
static const struct intel_padgroup tglh_community1_gpps[] = {
TGL_GPP(0, 79, 104, 128), /* GPP_D */
TGL_GPP(1, 105, 128, 160), /* GPP_C */
TGL_GPP(2, 129, 136, 192), /* GPP_S */
TGL_GPP(3, 137, 153, 224), /* GPP_G */
TGL_GPP(4, 154, 180, 256), /* vGPIO */
INTEL_GPP(0, 79, 104, 128), /* GPP_D */
INTEL_GPP(1, 105, 128, 160), /* GPP_C */
INTEL_GPP(2, 129, 136, 192), /* GPP_S */
INTEL_GPP(3, 137, 153, 224), /* GPP_G */
INTEL_GPP(4, 154, 180, 256), /* vGPIO */
};
static const struct intel_padgroup tglh_community3_gpps[] = {
TGL_GPP(0, 181, 193, 288), /* GPP_E */
TGL_GPP(1, 194, 217, 320), /* GPP_F */
INTEL_GPP(0, 181, 193, 288), /* GPP_E */
INTEL_GPP(1, 194, 217, 320), /* GPP_F */
};
static const struct intel_padgroup tglh_community4_gpps[] = {
TGL_GPP(0, 218, 241, 352), /* GPP_H */
TGL_GPP(1, 242, 251, 384), /* GPP_J */
TGL_GPP(2, 252, 266, 416), /* GPP_K */
INTEL_GPP(0, 218, 241, 352), /* GPP_H */
INTEL_GPP(1, 242, 251, 384), /* GPP_J */
INTEL_GPP(2, 252, 266, 416), /* GPP_K */
};
static const struct intel_padgroup tglh_community5_gpps[] = {
TGL_GPP(0, 267, 281, 448), /* GPP_I */
TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */
INTEL_GPP(0, 267, 281, 448), /* GPP_I */
INTEL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */
};
static const struct intel_community tglh_communities[] = {