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arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT

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usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Anson Huang
2019-10-16 10:14:23 +08:00
committed by Shawn Guo
parent bc66392d82
commit 3944b454f7
3 changed files with 8 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
View File

@@ -133,6 +133,8 @@ ethphy0: ethernet-phy@0 {
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
@@ -149,6 +151,8 @@ brcmf: wifi@1 {
/* SD */
&usdhc2 {
assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;

4
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@@ -137,6 +137,8 @@ light-sensor@44 {
};
&usdhc1 {
assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
@@ -147,6 +149,8 @@ &usdhc1 {
};
&usdhc2 {
assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;

6
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View File

@@ -368,8 +368,6 @@ usdhc1: mmc@5b010000 {
<&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
clock-names = "ipg", "per", "ahb";
assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
assigned-clock-rates = <200000000>;
power-domains = <&pd IMX_SC_R_SDHC_0>;
status = "disabled";
};
@@ -383,8 +381,6 @@ usdhc2: mmc@5b020000 {
<&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
clock-names = "ipg", "per", "ahb";
assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
assigned-clock-rates = <200000000>;
power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
@@ -400,8 +396,6 @@ usdhc3: mmc@5b030000 {
<&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
clock-names = "ipg", "per", "ahb";
assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
assigned-clock-rates = <200000000>;
power-domains = <&pd IMX_SC_R_SDHC_2>;
status = "disabled";
};