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soc: renesas: rz-sysc: Add SoC identification for RZ/V2N SoC

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Add SoC identification for the RZ/V2N SoC using the System Controller
(SYS) block.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250415085438.83856-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
2025-04-15 09:54:38 +01:00
committed by Geert Uytterhoeven
parent 5d6c7d34a8
commit 3903b4701b
5 changed files with 85 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/soc/renesas/Kconfig
View File

@@ -396,6 +396,7 @@ config ARCH_R9A09G047
config ARCH_R9A09G056
bool "ARM64 Platform support for RZ/V2N"
default y if ARCH_RENESAS
select SYS_R9A09G056
help
This enables support for the Renesas RZ/V2N SoC variants.
@@ -445,6 +446,10 @@ config SYS_R9A09G047
bool "Renesas RZ/G3E System controller support" if COMPILE_TEST
select SYSC_RZ
config SYS_R9A09G056
bool "Renesas RZ/V2N System controller support" if COMPILE_TEST
select SYSC_RZ
config SYS_R9A09G057
bool "Renesas RZ/V2H System controller support" if COMPILE_TEST
select SYSC_RZ

1
drivers/soc/renesas/Makefile
View File

@@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o
endif
obj-$(CONFIG_SYSC_R9A08G045) += r9a08g045-sysc.o
obj-$(CONFIG_SYS_R9A09G047) += r9a09g047-sys.o
obj-$(CONFIG_SYS_R9A09G056) += r9a09g056-sys.o
obj-$(CONFIG_SYS_R9A09G057) += r9a09g057-sys.o
# Family

75
drivers/soc/renesas/r9a09g056-sys.c Normal file
View File

@@ -0,0 +1,75 @@
// SPDX-License-Identifier: GPL-2.0
/*
* RZ/V2N System controller (SYS) driver
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include "rz-sysc.h"
/* Register Offsets */
#define SYS_LSI_MODE 0x300
#define SYS_LSI_MODE_SEC_EN BIT(16)
/*
* BOOTPLLCA[1:0]
* [0,0] => 1.1GHZ
* [0,1] => 1.5GHZ
* [1,0] => 1.6GHZ
* [1,1] => 1.7GHZ
*/
#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)
#define SYS_LSI_MODE_CA55_1_7GHZ 0x3
#define SYS_LSI_PRR 0x308
#define SYS_LSI_PRR_GPU_DIS BIT(0)
#define SYS_LSI_PRR_ISP_DIS BIT(4)
#define SYS_RZV2N_FEATURE_G31 BIT(0)
#define SYS_RZV2N_FEATURE_C55 BIT(1)
#define SYS_RZV2N_FEATURE_SEC BIT(2)
static void rzv2n_sys_print_id(struct device *dev,
void __iomem *sysc_base,
struct soc_device_attribute *soc_dev_attr)
{
u32 prr_val, mode_val;
u8 feature_flags;
prr_val = readl(sysc_base + SYS_LSI_PRR);
mode_val = readl(sysc_base + SYS_LSI_MODE);
/* Check GPU, ISP and Cryptographic configuration */
feature_flags = !(prr_val & SYS_LSI_PRR_GPU_DIS) ? SYS_RZV2N_FEATURE_G31 : 0;
feature_flags |= !(prr_val & SYS_LSI_PRR_ISP_DIS) ? SYS_RZV2N_FEATURE_C55 : 0;
feature_flags |= (mode_val & SYS_LSI_MODE_SEC_EN) ? SYS_RZV2N_FEATURE_SEC : 0;
dev_info(dev, "Detected Renesas %s %sn%d Rev %s%s%s%s%s\n", soc_dev_attr->family,
soc_dev_attr->soc_id, 41 + feature_flags, soc_dev_attr->revision,
feature_flags ? " with" : "",
feature_flags & SYS_RZV2N_FEATURE_G31 ? " GE3D (Mali-G31)" : "",
feature_flags & SYS_RZV2N_FEATURE_SEC ? " Cryptographic engine" : "",
feature_flags & SYS_RZV2N_FEATURE_C55 ? " ISP (Mali-C55)" : "");
/* Check CA55 PLL configuration */
if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
}
static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __initconst = {
.family = "RZ/V2N",
.id = 0x867d447,
.devid_offset = 0x304,
.revision_mask = GENMASK(31, 28),
.specific_id_mask = GENMASK(27, 0),
.print_id = rzv2n_sys_print_id,
};
const struct rz_sysc_init_data rzv2n_sys_init_data = {
.soc_id_init_data = &rzv2n_sys_soc_id_init_data,
};

3
drivers/soc/renesas/rz-sysc.c
View File

@@ -88,6 +88,9 @@ static const struct of_device_id rz_sysc_match[] = {
#ifdef CONFIG_SYS_R9A09G047
{ .compatible = "renesas,r9a09g047-sys", .data = &rzg3e_sys_init_data },
#endif
#ifdef CONFIG_SYS_R9A09G056
{ .compatible = "renesas,r9a09g056-sys", .data = &rzv2n_sys_init_data },
#endif
#ifdef CONFIG_SYS_R9A09G057
{ .compatible = "renesas,r9a09g057-sys", .data = &rzv2h_sys_init_data },
#endif

1
drivers/soc/renesas/rz-sysc.h
View File

@@ -42,5 +42,6 @@ struct rz_sysc_init_data {
extern const struct rz_sysc_init_data rzg3e_sys_init_data;
extern const struct rz_sysc_init_data rzg3s_sysc_init_data;
extern const struct rz_sysc_init_data rzv2h_sys_init_data;
extern const struct rz_sysc_init_data rzv2n_sys_init_data;
#endif /* __SOC_RENESAS_RZ_SYSC_H__ */