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Merge branch 'pci/controller/spacemit-k1'
- Add DT binding and driver for SpacemiT K1 (Alex Elder) * pci/controller/spacemit-k1: PCI: spacemit: Add SpacemiT PCIe host driver dt-bindings: pci: spacemit: Introduce PCIe host controller
This commit is contained in:
Bjorn Helgaas
157
Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
Normal file
157
Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
Normal file
@@ -0,0 +1,157 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SpacemiT K1 PCI Express Host Controller
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maintainers:
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- Alex Elder <elder@riscstar.com>
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description: >
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The SpacemiT K1 SoC PCIe host controller is based on the Synopsys DesignWare
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PCIe IP. The controller uses the DesignWare built-in MSI interrupt
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controller, and supports 256 MSIs.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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const: spacemit,k1-pcie
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reg:
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items:
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- description: DesignWare PCIe registers
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- description: ATU address space
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- description: PCIe configuration space
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- description: Link control registers
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reg-names:
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items:
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- const: dbi
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- const: atu
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- const: config
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- const: link
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clocks:
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items:
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- description: DWC PCIe Data Bus Interface (DBI) clock
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- description: DWC PCIe application AXI-bus master interface clock
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- description: DWC PCIe application AXI-bus slave interface clock
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clock-names:
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items:
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- const: dbi
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- const: mstr
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- const: slv
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resets:
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items:
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- description: DWC PCIe Data Bus Interface (DBI) reset
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- description: DWC PCIe application AXI-bus master interface reset
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- description: DWC PCIe application AXI-bus slave interface reset
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reset-names:
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items:
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- const: dbi
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- const: mstr
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- const: slv
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interrupts:
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items:
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- description: Interrupt used for MSIs
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interrupt-names:
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const: msi
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spacemit,apmu:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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A phandle that refers to the APMU system controller, whose regmap is
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used in managing resets and link state, along with and offset of its
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reset control register.
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items:
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- items:
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- description: phandle to APMU system controller
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- description: register offset
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patternProperties:
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'^pcie@':
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type: object
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$ref: /schemas/pci/pci-pci-bridge.yaml#
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properties:
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phys:
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maxItems: 1
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vpcie3v3-supply:
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description:
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A phandle for 3.3v regulator to use for PCIe
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required:
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- phys
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- vpcie3v3-supply
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unevaluatedProperties: false
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required:
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- clocks
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- clock-names
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- resets
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- reset-names
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- interrupts
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- interrupt-names
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- spacemit,apmu
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/spacemit,k1-syscon.h>
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pcie@ca400000 {
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device_type = "pci";
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compatible = "spacemit,k1-pcie";
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reg = <0xca400000 0x00001000>,
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<0xca700000 0x0001ff24>,
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<0x9f000000 0x00002000>,
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<0xc0c20000 0x00001000>;
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reg-names = "dbi",
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"atu",
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"config",
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"link";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x9f002000 0x0 0x00100000>,
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<0x02000000 0x0 0x90000000 0x90000000 0x0 0x0f000000>;
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interrupts = <142>;
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interrupt-names = "msi";
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clocks = <&syscon_apmu CLK_PCIE1_DBI>,
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<&syscon_apmu CLK_PCIE1_MASTER>,
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<&syscon_apmu CLK_PCIE1_SLAVE>;
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clock-names = "dbi",
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"mstr",
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"slv";
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resets = <&syscon_apmu RESET_PCIE1_DBI>,
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<&syscon_apmu RESET_PCIE1_MASTER>,
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<&syscon_apmu RESET_PCIE1_SLAVE>;
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reset-names = "dbi",
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"mstr",
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"slv";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_3_cfg>;
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spacemit,apmu = <&syscon_apmu 0x3d4>;
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pcie@0 {
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device_type = "pci";
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compatible = "pciclass,0604";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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phys = <&pcie1_phy>;
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vpcie3v3-supply = <&pcie_vcc_3v3>;
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};
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};
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@@ -426,6 +426,19 @@ config PCIE_SOPHGO_DW
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Say Y here if you want PCIe host controller support on
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Sophgo SoCs.
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config PCIE_SPACEMIT_K1
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tristate "SpacemiT K1 PCIe controller (host mode)"
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depends on ARCH_SPACEMIT || COMPILE_TEST
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depends on HAS_IOMEM
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select PCIE_DW_HOST
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select PCI_PWRCTRL_SLOT
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default ARCH_SPACEMIT
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help
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Enables support for the DesignWare based PCIe controller in
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the SpacemiT K1 SoC operating in host mode. Three controllers
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are available on the K1 SoC; the first of these shares a PHY
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with a USB 3.0 host controller (one or the other can be used).
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config PCIE_SPEAR13XX
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bool "STMicroelectronics SPEAr PCIe controller"
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depends on ARCH_SPEAR13XX || COMPILE_TEST
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@@ -35,6 +35,7 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
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obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
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obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
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obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
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obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o
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obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
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obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
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357
drivers/pci/controller/dwc/pcie-spacemit-k1.c
Normal file
357
drivers/pci/controller/dwc/pcie-spacemit-k1.c
Normal file
@@ -0,0 +1,357 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* SpacemiT K1 PCIe host driver
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*
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* Copyright (C) 2025 by RISCstar Solutions Corporation. All rights reserved.
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* Copyright (c) 2023, spacemit Corporation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/gfp.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mod_devicetable.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/types.h>
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#include "pcie-designware.h"
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#define PCI_VENDOR_ID_SPACEMIT 0x201f
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#define PCI_DEVICE_ID_SPACEMIT_K1 0x0001
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/* Offsets and field definitions for link management registers */
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#define K1_PHY_AHB_IRQ_EN 0x0000
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#define PCIE_INTERRUPT_EN BIT(0)
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#define K1_PHY_AHB_LINK_STS 0x0004
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#define SMLH_LINK_UP BIT(1)
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#define RDLH_LINK_UP BIT(12)
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#define INTR_ENABLE 0x0014
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#define MSI_CTRL_INT BIT(11)
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/* Some controls require APMU regmap access */
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#define SYSCON_APMU "spacemit,apmu"
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/* Offsets and field definitions for APMU registers */
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#define PCIE_CLK_RESET_CONTROL 0x0000
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#define LTSSM_EN BIT(6)
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#define PCIE_AUX_PWR_DET BIT(9)
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#define PCIE_RC_PERST BIT(12) /* 1: assert PERST# */
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#define APP_HOLD_PHY_RST BIT(30)
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#define DEVICE_TYPE_RC BIT(31) /* 0: endpoint; 1: RC */
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#define PCIE_CONTROL_LOGIC 0x0004
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#define PCIE_SOFT_RESET BIT(0)
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struct k1_pcie {
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struct dw_pcie pci;
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struct phy *phy;
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void __iomem *link;
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struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */
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u32 pmu_off;
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};
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#define to_k1_pcie(dw_pcie) \
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platform_get_drvdata(to_platform_device((dw_pcie)->dev))
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static void k1_pcie_toggle_soft_reset(struct k1_pcie *k1)
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{
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u32 offset;
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u32 val;
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/*
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* Write, then read back to guarantee it has reached the device
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* before we start the delay.
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*/
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offset = k1->pmu_off + PCIE_CONTROL_LOGIC;
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regmap_set_bits(k1->pmu, offset, PCIE_SOFT_RESET);
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regmap_read(k1->pmu, offset, &val);
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mdelay(2);
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regmap_clear_bits(k1->pmu, offset, PCIE_SOFT_RESET);
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}
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/* Enable app clocks, deassert resets */
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static int k1_pcie_enable_resources(struct k1_pcie *k1)
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{
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struct dw_pcie *pci = &k1->pci;
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int ret;
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ret = clk_bulk_prepare_enable(ARRAY_SIZE(pci->app_clks), pci->app_clks);
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if (ret)
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return ret;
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ret = reset_control_bulk_deassert(ARRAY_SIZE(pci->app_rsts),
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pci->app_rsts);
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if (ret)
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goto err_disable_clks;
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return 0;
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err_disable_clks:
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clk_bulk_disable_unprepare(ARRAY_SIZE(pci->app_clks), pci->app_clks);
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return ret;
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}
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/* Assert resets, disable app clocks */
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static void k1_pcie_disable_resources(struct k1_pcie *k1)
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{
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struct dw_pcie *pci = &k1->pci;
|
||||
|
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reset_control_bulk_assert(ARRAY_SIZE(pci->app_rsts), pci->app_rsts);
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clk_bulk_disable_unprepare(ARRAY_SIZE(pci->app_clks), pci->app_clks);
|
||||
}
|
||||
|
||||
/* FIXME: Disable ASPM L1 to avoid errors reported on some NVMe drives */
|
||||
static void k1_pcie_disable_aspm_l1(struct k1_pcie *k1)
|
||||
{
|
||||
struct dw_pcie *pci = &k1->pci;
|
||||
u8 offset;
|
||||
u32 val;
|
||||
|
||||
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
|
||||
offset += PCI_EXP_LNKCAP;
|
||||
|
||||
dw_pcie_dbi_ro_wr_en(pci);
|
||||
val = dw_pcie_readl_dbi(pci, offset);
|
||||
val &= ~PCI_EXP_LNKCAP_ASPM_L1;
|
||||
dw_pcie_writel_dbi(pci, offset, val);
|
||||
dw_pcie_dbi_ro_wr_dis(pci);
|
||||
}
|
||||
|
||||
static int k1_pcie_init(struct dw_pcie_rp *pp)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
struct k1_pcie *k1 = to_k1_pcie(pci);
|
||||
u32 reset_ctrl;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
k1_pcie_toggle_soft_reset(k1);
|
||||
|
||||
ret = k1_pcie_enable_resources(k1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Set the PCI vendor and device ID */
|
||||
dw_pcie_dbi_ro_wr_en(pci);
|
||||
dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_SPACEMIT);
|
||||
dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_SPACEMIT_K1);
|
||||
dw_pcie_dbi_ro_wr_dis(pci);
|
||||
|
||||
/*
|
||||
* Start by asserting fundamental reset (drive PERST# low). The
|
||||
* PCI CEM spec says that PERST# should be deasserted at least
|
||||
* 100ms after the power becomes stable, so we'll insert that
|
||||
* delay first. Write, then read it back to guarantee the write
|
||||
* reaches the device before we start the delay.
|
||||
*/
|
||||
reset_ctrl = k1->pmu_off + PCIE_CLK_RESET_CONTROL;
|
||||
regmap_set_bits(k1->pmu, reset_ctrl, PCIE_RC_PERST);
|
||||
regmap_read(k1->pmu, reset_ctrl, &val);
|
||||
mdelay(PCIE_T_PVPERL_MS);
|
||||
|
||||
/*
|
||||
* Put the controller in root complex mode, and indicate that
|
||||
* Vaux (3.3v) is present.
|
||||
*/
|
||||
regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET);
|
||||
|
||||
ret = phy_init(k1->phy);
|
||||
if (ret) {
|
||||
k1_pcie_disable_resources(k1);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Deassert fundamental reset (drive PERST# high) */
|
||||
regmap_clear_bits(k1->pmu, reset_ctrl, PCIE_RC_PERST);
|
||||
|
||||
/* Finally, as a workaround, disable ASPM L1 */
|
||||
k1_pcie_disable_aspm_l1(k1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void k1_pcie_deinit(struct dw_pcie_rp *pp)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
struct k1_pcie *k1 = to_k1_pcie(pci);
|
||||
|
||||
/* Assert fundamental reset (drive PERST# low) */
|
||||
regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL,
|
||||
PCIE_RC_PERST);
|
||||
|
||||
phy_exit(k1->phy);
|
||||
|
||||
k1_pcie_disable_resources(k1);
|
||||
}
|
||||
|
||||
static const struct dw_pcie_host_ops k1_pcie_host_ops = {
|
||||
.init = k1_pcie_init,
|
||||
.deinit = k1_pcie_deinit,
|
||||
};
|
||||
|
||||
static bool k1_pcie_link_up(struct dw_pcie *pci)
|
||||
{
|
||||
struct k1_pcie *k1 = to_k1_pcie(pci);
|
||||
u32 val;
|
||||
|
||||
val = readl_relaxed(k1->link + K1_PHY_AHB_LINK_STS);
|
||||
|
||||
return (val & RDLH_LINK_UP) && (val & SMLH_LINK_UP);
|
||||
}
|
||||
|
||||
static int k1_pcie_start_link(struct dw_pcie *pci)
|
||||
{
|
||||
struct k1_pcie *k1 = to_k1_pcie(pci);
|
||||
u32 val;
|
||||
|
||||
/* Stop holding the PHY in reset, and enable link training */
|
||||
regmap_update_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL,
|
||||
APP_HOLD_PHY_RST | LTSSM_EN, LTSSM_EN);
|
||||
|
||||
/* Enable the MSI interrupt */
|
||||
writel_relaxed(MSI_CTRL_INT, k1->link + INTR_ENABLE);
|
||||
|
||||
/* Top-level interrupt enable */
|
||||
val = readl_relaxed(k1->link + K1_PHY_AHB_IRQ_EN);
|
||||
val |= PCIE_INTERRUPT_EN;
|
||||
writel_relaxed(val, k1->link + K1_PHY_AHB_IRQ_EN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void k1_pcie_stop_link(struct dw_pcie *pci)
|
||||
{
|
||||
struct k1_pcie *k1 = to_k1_pcie(pci);
|
||||
u32 val;
|
||||
|
||||
/* Disable interrupts */
|
||||
val = readl_relaxed(k1->link + K1_PHY_AHB_IRQ_EN);
|
||||
val &= ~PCIE_INTERRUPT_EN;
|
||||
writel_relaxed(val, k1->link + K1_PHY_AHB_IRQ_EN);
|
||||
|
||||
writel_relaxed(0, k1->link + INTR_ENABLE);
|
||||
|
||||
/* Disable the link and hold the PHY in reset */
|
||||
regmap_update_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL,
|
||||
APP_HOLD_PHY_RST | LTSSM_EN, APP_HOLD_PHY_RST);
|
||||
}
|
||||
|
||||
static const struct dw_pcie_ops k1_pcie_ops = {
|
||||
.link_up = k1_pcie_link_up,
|
||||
.start_link = k1_pcie_start_link,
|
||||
.stop_link = k1_pcie_stop_link,
|
||||
};
|
||||
|
||||
static int k1_pcie_parse_port(struct k1_pcie *k1)
|
||||
{
|
||||
struct device *dev = k1->pci.dev;
|
||||
struct device_node *root_port;
|
||||
struct phy *phy;
|
||||
|
||||
/* We assume only one root port */
|
||||
root_port = of_get_next_available_child(dev_of_node(dev), NULL);
|
||||
if (!root_port)
|
||||
return -EINVAL;
|
||||
|
||||
phy = devm_of_phy_get(dev, root_port, NULL);
|
||||
|
||||
of_node_put(root_port);
|
||||
|
||||
if (IS_ERR(phy))
|
||||
return PTR_ERR(phy);
|
||||
|
||||
k1->phy = phy;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int k1_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct k1_pcie *k1;
|
||||
int ret;
|
||||
|
||||
k1 = devm_kzalloc(dev, sizeof(*k1), GFP_KERNEL);
|
||||
if (!k1)
|
||||
return -ENOMEM;
|
||||
|
||||
k1->pmu = syscon_regmap_lookup_by_phandle_args(dev_of_node(dev),
|
||||
SYSCON_APMU, 1,
|
||||
&k1->pmu_off);
|
||||
if (IS_ERR(k1->pmu))
|
||||
return dev_err_probe(dev, PTR_ERR(k1->pmu),
|
||||
"failed to lookup PMU registers\n");
|
||||
|
||||
k1->link = devm_platform_ioremap_resource_byname(pdev, "link");
|
||||
if (IS_ERR(k1->link))
|
||||
return dev_err_probe(dev, PTR_ERR(k1->link),
|
||||
"failed to map \"link\" registers\n");
|
||||
|
||||
k1->pci.dev = dev;
|
||||
k1->pci.ops = &k1_pcie_ops;
|
||||
k1->pci.pp.num_vectors = MAX_MSI_IRQS;
|
||||
dw_pcie_cap_set(&k1->pci, REQ_RES);
|
||||
|
||||
k1->pci.pp.ops = &k1_pcie_host_ops;
|
||||
|
||||
/* Hold the PHY in reset until we start the link */
|
||||
regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL,
|
||||
APP_HOLD_PHY_RST);
|
||||
|
||||
ret = devm_regulator_get_enable(dev, "vpcie3v3");
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret,
|
||||
"failed to get \"vpcie3v3\" supply\n");
|
||||
|
||||
pm_runtime_set_active(dev);
|
||||
pm_runtime_no_callbacks(dev);
|
||||
devm_pm_runtime_enable(dev);
|
||||
|
||||
platform_set_drvdata(pdev, k1);
|
||||
|
||||
ret = k1_pcie_parse_port(k1);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to parse root port\n");
|
||||
|
||||
ret = dw_pcie_host_init(&k1->pci.pp);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to initialize host\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void k1_pcie_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct k1_pcie *k1 = platform_get_drvdata(pdev);
|
||||
|
||||
dw_pcie_host_deinit(&k1->pci.pp);
|
||||
}
|
||||
|
||||
static const struct of_device_id k1_pcie_of_match_table[] = {
|
||||
{ .compatible = "spacemit,k1-pcie", },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver k1_pcie_driver = {
|
||||
.probe = k1_pcie_probe,
|
||||
.remove = k1_pcie_remove,
|
||||
.driver = {
|
||||
.name = "spacemit-k1-pcie",
|
||||
.of_match_table = k1_pcie_of_match_table,
|
||||
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
||||
},
|
||||
};
|
||||
module_platform_driver(k1_pcie_driver);
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("SpacemiT K1 PCIe host driver");
|
||||
Reference in New Issue
Block a user