drm/i915/dpt: move suspend/resume to parent interface

Add per-vm DPT suspend/resume calls to the display parent interface, and
lift the generic code away from i915 specific code.

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Link: https://patch.msgid.link/080945a49559ec1f5183ad409e1526736e828d90.1772030909.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2026-02-25 16:49:10 +02:00
parent 2a62dc7472
commit 3834ea7499
8 changed files with 91 additions and 64 deletions

View File

@@ -10,13 +10,10 @@
struct i915_address_space;
struct i915_vma;
struct intel_display;
struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm,
unsigned int alignment);
void intel_dpt_unpin_from_ggtt(struct i915_address_space *vm);
void intel_dpt_suspend(struct intel_display *display);
void intel_dpt_resume(struct intel_display *display);
u64 intel_dpt_offset(struct i915_vma *dpt_vma);
#endif /* __INTEL_DPT_H__ */

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@@ -7,6 +7,7 @@
#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dpt_common.h"
#include "intel_parent.h"
#include "skl_universal_plane_regs.h"
void intel_dpt_configure(struct intel_crtc *crtc)
@@ -33,3 +34,61 @@ void intel_dpt_configure(struct intel_crtc *crtc)
CHICKEN_MISC_DISABLE_DPT);
}
}
/**
* intel_dpt_suspend - suspend the memory mapping for all DPT FBs during system suspend
* @display: display device instance
*
* Suspend the memory mapping during system suspend for all framebuffers which
* are mapped to HW via a GGTT->DPT page table.
*
* This function must be called before the mappings in GGTT are suspended calling
* i915_ggtt_suspend().
*/
void intel_dpt_suspend(struct intel_display *display)
{
struct drm_framebuffer *drm_fb;
if (!HAS_DISPLAY(display))
return;
mutex_lock(&display->drm->mode_config.fb_lock);
drm_for_each_fb(drm_fb, display->drm) {
struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
if (fb->dpt_vm)
intel_parent_dpt_suspend(display, fb->dpt_vm);
}
mutex_unlock(&display->drm->mode_config.fb_lock);
}
/**
* intel_dpt_resume - restore the memory mapping for all DPT FBs during system resume
* @display: display device instance
*
* Restore the memory mapping during system resume for all framebuffers which
* are mapped to HW via a GGTT->DPT page table. The content of these page
* tables are not stored in the hibernation image during S4 and S3RST->S4
* transitions, so here we reprogram the PTE entries in those tables.
*
* This function must be called after the mappings in GGTT have been restored calling
* i915_ggtt_resume().
*/
void intel_dpt_resume(struct intel_display *display)
{
struct drm_framebuffer *drm_fb;
if (!HAS_DISPLAY(display))
return;
mutex_lock(&display->drm->mode_config.fb_lock);
drm_for_each_fb(drm_fb, display->drm) {
struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
if (fb->dpt_vm)
intel_parent_dpt_resume(display, fb->dpt_vm);
}
mutex_unlock(&display->drm->mode_config.fb_lock);
}

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@@ -7,7 +7,10 @@
#define __INTEL_DPT_COMMON_H__
struct intel_crtc;
struct intel_display;
void intel_dpt_configure(struct intel_crtc *crtc);
void intel_dpt_suspend(struct intel_display *display);
void intel_dpt_resume(struct intel_display *display);
#endif /* __INTEL_DPT_COMMON_H__ */

View File

@@ -40,6 +40,18 @@ void intel_parent_dpt_destroy(struct intel_display *display, struct i915_address
display->parent->dpt->destroy(vm);
}
void intel_parent_dpt_suspend(struct intel_display *display, struct i915_address_space *vm)
{
if (display->parent->dpt)
display->parent->dpt->suspend(vm);
}
void intel_parent_dpt_resume(struct intel_display *display, struct i915_address_space *vm)
{
if (display->parent->dpt)
display->parent->dpt->resume(vm);
}
/* hdcp */
ssize_t intel_parent_hdcp_gsc_msg_send(struct intel_display *display,
struct intel_hdcp_gsc_context *gsc_context,

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@@ -20,6 +20,8 @@ struct i915_address_space *intel_parent_dpt_create(struct intel_display *display
struct drm_gem_object *obj,
size_t size);
void intel_parent_dpt_destroy(struct intel_display *display, struct i915_address_space *vm);
void intel_parent_dpt_suspend(struct intel_display *display, struct i915_address_space *vm);
void intel_parent_dpt_resume(struct intel_display *display, struct i915_address_space *vm);
/* hdcp */
ssize_t intel_parent_hdcp_gsc_msg_send(struct intel_display *display,

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@@ -8,9 +8,7 @@
#include "display/intel_display_core.h"
#include "display/intel_display_rpm.h"
#include "display/intel_display_types.h"
#include "display/intel_dpt.h"
#include "display/intel_fb.h"
#include "gem/i915_gem_domain.h"
#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_lmem.h"
@@ -185,64 +183,6 @@ void intel_dpt_unpin_from_ggtt(struct i915_address_space *vm)
i915_vma_put(dpt->vma);
}
/**
* intel_dpt_resume - restore the memory mapping for all DPT FBs during system resume
* @display: display device instance
*
* Restore the memory mapping during system resume for all framebuffers which
* are mapped to HW via a GGTT->DPT page table. The content of these page
* tables are not stored in the hibernation image during S4 and S3RST->S4
* transitions, so here we reprogram the PTE entries in those tables.
*
* This function must be called after the mappings in GGTT have been restored calling
* i915_ggtt_resume().
*/
void intel_dpt_resume(struct intel_display *display)
{
struct drm_framebuffer *drm_fb;
if (!HAS_DISPLAY(display))
return;
mutex_lock(&display->drm->mode_config.fb_lock);
drm_for_each_fb(drm_fb, display->drm) {
struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
if (fb->dpt_vm)
i915_ggtt_resume_vm(fb->dpt_vm, true);
}
mutex_unlock(&display->drm->mode_config.fb_lock);
}
/**
* intel_dpt_suspend - suspend the memory mapping for all DPT FBs during system suspend
* @display: display device instance
*
* Suspend the memory mapping during system suspend for all framebuffers which
* are mapped to HW via a GGTT->DPT page table.
*
* This function must be called before the mappings in GGTT are suspended calling
* i915_ggtt_suspend().
*/
void intel_dpt_suspend(struct intel_display *display)
{
struct drm_framebuffer *drm_fb;
if (!HAS_DISPLAY(display))
return;
mutex_lock(&display->drm->mode_config.fb_lock);
drm_for_each_fb(drm_fb, display->drm) {
struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
if (fb->dpt_vm)
i915_ggtt_suspend_vm(fb->dpt_vm, true);
}
mutex_unlock(&display->drm->mode_config.fb_lock);
}
static struct i915_address_space *i915_dpt_create(struct drm_gem_object *obj, size_t size)
{
struct drm_i915_private *i915 = to_i915(obj->dev);
@@ -316,6 +256,16 @@ static void i915_dpt_destroy(struct i915_address_space *vm)
i915_vm_put(&dpt->vm);
}
static void i915_dpt_suspend(struct i915_address_space *vm)
{
i915_ggtt_suspend_vm(vm, true);
}
static void i915_dpt_resume(struct i915_address_space *vm)
{
i915_ggtt_resume_vm(vm, true);
}
u64 intel_dpt_offset(struct i915_vma *dpt_vma)
{
return i915_vma_offset(dpt_vma);
@@ -324,4 +274,6 @@ u64 intel_dpt_offset(struct i915_vma *dpt_vma)
const struct intel_display_dpt_interface i915_display_dpt_interface = {
.create = i915_dpt_create,
.destroy = i915_dpt_destroy,
.suspend = i915_dpt_suspend,
.resume = i915_dpt_resume,
};

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@@ -59,7 +59,7 @@
#include "display/intel_display_power.h"
#include "display/intel_dmc.h"
#include "display/intel_dp.h"
#include "display/intel_dpt.h"
#include "display/intel_dpt_common.h"
#include "display/intel_dram.h"
#include "display/intel_encoder.h"
#include "display/intel_fbdev.h"

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@@ -27,6 +27,8 @@ struct ref_tracker;
struct intel_display_dpt_interface {
struct i915_address_space *(*create)(struct drm_gem_object *obj, size_t size);
void (*destroy)(struct i915_address_space *vm);
void (*suspend)(struct i915_address_space *vm);
void (*resume)(struct i915_address_space *vm);
};
struct intel_display_dsb_interface {