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staging: comedi: ni_stc.h: tidy up AO_Command_2_Register and bits
Rename the CamelCase. Use the BIT() macro to define the bits. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
a1da35a5c5
commit
382b3c4f9a
@@ -317,7 +317,7 @@ static const struct mio_regmap m_series_stc_write_regmap[] = {
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[NISTC_INTA_ACK_REG] = { 0x104, 2 },
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[NISTC_INTB_ACK_REG] = { 0x106, 2 },
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[NISTC_AI_CMD2_REG] = { 0x108, 2 },
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[AO_Command_2_Register] = { 0x10a, 2 },
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[NISTC_AO_CMD2_REG] = { 0x10a, 2 },
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[G_Command_Register(0)] = { 0x10c, 2 },
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[G_Command_Register(1)] = { 0x10e, 2 },
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[AI_Command_1_Register] = { 0x110, 2 },
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@@ -2909,8 +2909,8 @@ static int ni_ao_inttrig(struct comedi_device *dev,
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AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
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AO_Command_1_Register);
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ni_stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
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AO_Command_2_Register);
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ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
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NISTC_AO_CMD2_REG);
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return 0;
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}
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@@ -3024,7 +3024,7 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
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switch (cmd->scan_begin_src) {
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case TRIG_TIMER:
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devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
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devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
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trigvar =
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ni_ns_to_timer(dev, cmd->scan_begin_arg,
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CMDF_ROUND_NEAREST);
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@@ -3037,13 +3037,13 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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AO_UPDATE_Source_Select(cmd->scan_begin_arg);
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if (cmd->scan_begin_arg & CR_INVERT)
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devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
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devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
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devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
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break;
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default:
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BUG();
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break;
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}
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ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
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ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
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ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
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devpriv->ao_mode2 &=
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~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
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@@ -3216,7 +3216,7 @@ static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
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devpriv->ao_cmd1 = 0;
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ni_stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
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devpriv->ao_cmd2 = 0;
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ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
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ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
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devpriv->ao_mode1 = 0;
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ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
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devpriv->ao_mode2 = 0;
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@@ -109,6 +109,23 @@
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#define NISTC_AI_CMD2_START2_PULSE BIT(1)
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#define NISTC_AI_CMD2_START1_PULSE BIT(0)
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#define NISTC_AO_CMD2_REG 5
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#define NISTC_AO_CMD2_END_ON_BC_TC(x) (((x) & 0x3) << 14)
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#define NISTC_AO_CMD2_START_STOP_GATE_ENA BIT(13)
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#define NISTC_AO_CMD2_UC_SAVE_TRACE BIT(12)
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#define NISTC_AO_CMD2_BC_GATE_ENA BIT(11)
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#define NISTC_AO_CMD2_BC_SAVE_TRACE BIT(10)
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#define NISTC_AO_CMD2_UI_SW_ON_BC_TC BIT(9)
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#define NISTC_AO_CMD2_UI_SW_ON_STOP BIT(8)
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#define NISTC_AO_CMD2_UI_SW_ON_TC BIT(7)
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#define NISTC_AO_CMD2_UC_SW_ON_BC_TC BIT(6)
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#define NISTC_AO_CMD2_UC_SW_ON_TC BIT(5)
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#define NISTC_AO_CMD2_BC_SW_ON_TC BIT(4)
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#define NISTC_AO_CMD2_MUTE_B BIT(3)
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#define NISTC_AO_CMD2_MUTE_A BIT(2)
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#define NISTC_AO_CMD2_UPDATE2_PULSE BIT(1)
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#define NISTC_AO_CMD2_START1_PULSE BIT(0)
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#define AI_Status_1_Register 2
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#define Interrupt_A_St 0x8000
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#define AI_FIFO_Full_St 0x4000
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@@ -147,23 +164,6 @@
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#define AO_FIFO_Request_St _bit1
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#define Pass_Thru_1_Interrupt_St _bit0
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#define AO_Command_2_Register 5
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#define AO_End_On_BC_TC(x) (((x) & 0x3) << 14)
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#define AO_Start_Stop_Gate_Enable _bit13
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#define AO_UC_Save_Trace _bit12
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#define AO_BC_Gate_Enable _bit11
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#define AO_BC_Save_Trace _bit10
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#define AO_UI_Switch_Load_On_BC_TC _bit9
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#define AO_UI_Switch_Load_On_Stop _bit8
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#define AO_UI_Switch_Load_On_TC _bit7
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#define AO_UC_Switch_Load_On_BC_TC _bit6
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#define AO_UC_Switch_Load_On_TC _bit5
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#define AO_BC_Switch_Load_On_TC _bit4
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#define AO_Mute_B _bit3
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#define AO_Mute_A _bit2
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#define AO_UPDATE2_Pulse _bit1
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#define AO_START1_Pulse _bit0
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#define AO_Status_2_Register 6
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#define DIO_Parallel_Input_Register 7
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