iommu/io-pgtable-arm: Add coverage for different OAS in selftest

Run selftests with different OAS values intead of hardcoding it to 48
bits.

We always keep OAS >= IAS to make the config valid for stage-2.

This can be further improved, if we split IAS/OAS configuration for
stage-1 and stage-2 (to use input sizes compatible with VA_BITS as
SMMUv3 does, or IAS > OAS which is valid for stage-1).

However, that adds more complexity, and the current change improves
coverage and makes it possible to test all concatenation cases.

Signed-off-by: Mostafa Saleh <smostafa@google.com>
Link: https://lore.kernel.org/r/20241202140604.422235-3-smostafa@google.com
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Mostafa Saleh
2024-12-02 14:06:04 +00:00
committed by Will Deacon
parent 4dcac8407f
commit 376ce8b35e

View File

@@ -1385,15 +1385,14 @@ static int __init arm_lpae_do_selftests(void)
SZ_64K | SZ_512M,
};
static const unsigned int ias[] __initconst = {
static const unsigned int address_size[] __initconst = {
32, 36, 40, 42, 44, 48,
};
int i, j, pass = 0, fail = 0;
int i, j, k, pass = 0, fail = 0;
struct device dev;
struct io_pgtable_cfg cfg = {
.tlb = &dummy_tlb_ops,
.oas = 48,
.coherent_walk = true,
.iommu_dev = &dev,
};
@@ -1402,15 +1401,19 @@ static int __init arm_lpae_do_selftests(void)
set_dev_node(&dev, NUMA_NO_NODE);
for (i = 0; i < ARRAY_SIZE(pgsize); ++i) {
for (j = 0; j < ARRAY_SIZE(ias); ++j) {
cfg.pgsize_bitmap = pgsize[i];
cfg.ias = ias[j];
pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n",
pgsize[i], ias[j]);
if (arm_lpae_run_tests(&cfg))
fail++;
else
pass++;
for (j = 0; j < ARRAY_SIZE(address_size); ++j) {
/* Don't use ias > oas as it is not valid for stage-2. */
for (k = 0; k <= j; ++k) {
cfg.pgsize_bitmap = pgsize[i];
cfg.ias = address_size[k];
cfg.oas = address_size[j];
pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u OAS %u\n",
pgsize[i], cfg.ias, cfg.oas);
if (arm_lpae_run_tests(&cfg))
fail++;
else
pass++;
}
}
}