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drm/amd/display: Silence type conversion warnings in dml2

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[Why]
Compiler build generates type conversion warnings throughout dc/dml2_0
where values are implicitly narrowed (e.g. int/uint32_t/uint64_t assigned
to uint8_t, unsigned char, char, bool, or dml_bool_t), cluttering build
output and masking genuine issues.

[How]
Add explicit casts at each narrowing assignment with ASSERT guards
to catch out-of-range values in debug builds:
- uint8_t: otg_inst, num_planes, pipe_idx, vblank_index fields
- unsigned char: pipe_dlg_param.otg_inst from tg->inst
- char: mcache num_pipes from num_dpps_required
- bool/dml_bool_t: INTERLACE bitfield and fams2 enable flag use != 0
- uint64_t: widen min_hardware_refresh_in_uhz to hold div64_u64 result,
  then cast to unsigned long for min_refresh_uhz with ASSERT

Reviewed-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Gaghik Khachatrian
2026-03-16 11:34:49 -04:00
committed by Alex Deucher
parent c3f327a9a3
commit 3722df98c2
7 changed files with 41 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
View File

@@ -90,7 +90,8 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf
struct pipe_ctx *pipe_ctx,
struct dml2_context *dml_ctx)
{
unsigned int hblank_start, vblank_start, min_hardware_refresh_in_uhz;
unsigned int hblank_start, vblank_start;
uint64_t min_hardware_refresh_in_uhz;
uint32_t pix_clk_100hz;
timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding;
@@ -105,7 +106,7 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf
timing->h_total = stream->timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding;
timing->v_total = stream->timing.v_total;
timing->h_sync_width = stream->timing.h_sync_width;
timing->interlaced = stream->timing.flags.INTERLACE;
timing->interlaced = (stream->timing.flags.INTERLACE != 0);
hblank_start = stream->timing.h_total - stream->timing.h_front_porch;
@@ -137,7 +138,11 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf
(timing->h_total * (long long)calc_max_hardware_v_total(stream)));
}
timing->drr_config.min_refresh_uhz = max(stream->timing.min_refresh_in_uhz, min_hardware_refresh_in_uhz);
{
uint64_t min_refresh = max((uint64_t)stream->timing.min_refresh_in_uhz, min_hardware_refresh_in_uhz);
ASSERT(min_refresh <= ULONG_MAX);
timing->drr_config.min_refresh_uhz = (unsigned long)min_refresh;
}
if (dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase &&
stream->ctx->dc->config.enable_fpo_flicker_detection == 1)
@@ -697,7 +702,7 @@ unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx,
if (!dml21_wrapper_get_plane_id(context, stream_id, plane, &plane_id)) {
ASSERT(false);
return -1;
return UINT_MAX;
}
for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {

15
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
View File

@@ -420,8 +420,12 @@ static unsigned int dml21_build_fams2_stream_programming_v2(const struct dc *dc,
type = static_base_state->stream_v1.base.type;
/* get information from context */
static_base_state->stream_v1.base.num_planes = context->stream_status[dc_stream_idx].plane_count;
static_base_state->stream_v1.base.otg_inst = context->stream_status[dc_stream_idx].primary_otg_inst;
ASSERT(context->stream_status[dc_stream_idx].plane_count >= 0 &&
context->stream_status[dc_stream_idx].plane_count <= 0xFF);
ASSERT(context->stream_status[dc_stream_idx].primary_otg_inst >= 0 &&
context->stream_status[dc_stream_idx].primary_otg_inst <= 0xFF);
static_base_state->stream_v1.base.num_planes = (uint8_t)context->stream_status[dc_stream_idx].plane_count;
static_base_state->stream_v1.base.otg_inst = (uint8_t)context->stream_status[dc_stream_idx].primary_otg_inst;
/* populate pipe masks for planes */
for (dc_plane_idx = 0; dc_plane_idx < context->stream_status[dc_stream_idx].plane_count; dc_plane_idx++) {
@@ -458,7 +462,9 @@ static unsigned int dml21_build_fams2_stream_programming_v2(const struct dc *dc,
switch (dc->debug.fams_version.minor) {
case 1:
default:
static_sub_state->stream_v1.sub_state.subvp.phantom_otg_inst = phantom_status->primary_otg_inst;
ASSERT(phantom_status->primary_otg_inst >= 0 &&
phantom_status->primary_otg_inst <= 0xFF);
static_sub_state->stream_v1.sub_state.subvp.phantom_otg_inst = (uint8_t)phantom_status->primary_otg_inst;
/* populate pipe masks for phantom planes */
for (dc_plane_idx = 0; dc_plane_idx < phantom_status->plane_count; dc_plane_idx++) {
@@ -516,7 +522,8 @@ void dml21_build_fams2_programming(const struct dc *dc,
context->bw_ctx.bw.dcn.fams2_global_config.num_streams = num_fams2_streams;
}
context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;
context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching =
(context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable != 0);
}
bool dml21_is_plane1_enabled(enum dml2_source_format_class source_format)

6
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c
View File

@@ -297,7 +297,8 @@ void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context
memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));
mcache_config->plane_descriptor = pln_prog->plane_descriptor;
mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx];
mcache_config->num_pipes = pln_prog->num_dpps_required;
ASSERT(pln_prog->num_dpps_required <= 0x7F);
mcache_config->num_pipes = (char)pln_prog->num_dpps_required;
l->build_mcache_programming_params.num_configurations++;
if (pln_prog->num_dpps_required == 0) {
@@ -324,7 +325,8 @@ void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context
memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));
mcache_config->plane_descriptor = pln_prog->plane_descriptor;
mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx];
mcache_config->num_pipes = pln_prog->num_dpps_required;
ASSERT(pln_prog->num_dpps_required <= 0x7F);
mcache_config->num_pipes = (char)pln_prog->num_dpps_required;
l->build_mcache_programming_params.num_configurations++;
for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {

18
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c
View File

@@ -366,7 +366,8 @@ static bool find_more_pipes_for_stream(struct dml2_context *ctx,
if (!is_plane_using_pipe(pipe)) {
pipes_needed--;
// TODO: This doens't make sense really, pipe_idx should always be valid
pipe->pipe_idx = preferred_pipe_candidates[i];
ASSERT(preferred_pipe_candidates[i] <= 0xFF);
pipe->pipe_idx = (uint8_t)preferred_pipe_candidates[i];
assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx;
}
}
@@ -382,7 +383,8 @@ static bool find_more_pipes_for_stream(struct dml2_context *ctx,
if (!is_plane_using_pipe(pipe)) {
pipes_needed--;
// TODO: This doens't make sense really, pipe_idx should always be valid
pipe->pipe_idx = i;
ASSERT(i >= 0 && i <= 0xFF);
pipe->pipe_idx = (uint8_t)i;
assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx;
}
}
@@ -393,7 +395,8 @@ static bool find_more_pipes_for_stream(struct dml2_context *ctx,
if (!is_plane_using_pipe(pipe)) {
pipes_needed--;
// TODO: This doens't make sense really, pipe_idx should always be valid
pipe->pipe_idx = last_resort_pipe_candidates[i];
ASSERT(last_resort_pipe_candidates[i] <= 0xFF);
pipe->pipe_idx = (uint8_t)last_resort_pipe_candidates[i];
assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx;
}
}
@@ -432,7 +435,8 @@ static bool find_more_free_pipes(struct dml2_context *ctx,
if (is_pipe_free(pipe)) {
pipes_needed--;
// TODO: This doens't make sense really, pipe_idx should always be valid
pipe->pipe_idx = preferred_pipe_candidates[i];
ASSERT(preferred_pipe_candidates[i] <= 0xFF);
pipe->pipe_idx = (uint8_t)preferred_pipe_candidates[i];
assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx;
}
}
@@ -448,7 +452,8 @@ static bool find_more_free_pipes(struct dml2_context *ctx,
if (is_pipe_free(pipe)) {
pipes_needed--;
// TODO: This doens't make sense really, pipe_idx should always be valid
pipe->pipe_idx = i;
ASSERT(i >= 0 && i <= 0xFF);
pipe->pipe_idx = (uint8_t)i;
assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx;
}
}
@@ -459,7 +464,8 @@ static bool find_more_free_pipes(struct dml2_context *ctx,
if (is_pipe_free(pipe)) {
pipes_needed--;
// TODO: This doens't make sense really, pipe_idx should always be valid
pipe->pipe_idx = last_resort_pipe_candidates[i];
ASSERT(last_resort_pipe_candidates[i] <= 0xFF);
pipe->pipe_idx = (uint8_t)last_resort_pipe_candidates[i];
assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx;
}
}

3
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
View File

@@ -555,7 +555,8 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state *
if (!found && pipe_mall_type == SUBVP_NONE) {
// Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).
vblank_index = i;
ASSERT(i <= 0xFF);
vblank_index = (uint8_t)i;
found = true;
}

2
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
View File

@@ -765,7 +765,7 @@ static void populate_dml_timing_cfg_from_stream_state(struct dml_timing_cfg_st *
out->PixelClock[location] *= 2;
out->HTotal[location] = in->timing.h_total;
out->VTotal[location] = in->timing.v_total;
out->Interlace[location] = in->timing.flags.INTERLACE;
out->Interlace[location] = (in->timing.flags.INTERLACE != 0);
hblank_start = in->timing.h_total - in->timing.h_front_porch;
out->HBlankEnd[location] = hblank_start
- in->timing.h_addressable

3
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
View File

@@ -255,7 +255,8 @@ static void populate_pipe_ctx_dlg_params_from_dml(struct pipe_ctx *pipe_ctx, str
pipe_ctx->pipe_dlg_param.vupdate_width = dml_get_vupdate_width(mode_lib, pipe_idx);
pipe_ctx->pipe_dlg_param.vready_offset = dml_get_vready_offset(mode_lib, pipe_idx);
pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst;
ASSERT(pipe_ctx->stream_res.tg->inst >= 0 && pipe_ctx->stream_res.tg->inst <= 0xFF);
pipe_ctx->pipe_dlg_param.otg_inst = (unsigned char)pipe_ctx->stream_res.tg->inst;
pipe_ctx->pipe_dlg_param.hactive = hactive;
pipe_ctx->pipe_dlg_param.vactive = vactive;