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ARM: dts: ixp4xx: Add Arcom Vulcan device tree
This adds a device tree for the Arcom Vulcan IXP42x board. Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
@@ -245,7 +245,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
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intel-ixp42x-iomega-nas100d.dtb \
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intel-ixp42x-dlink-dsm-g600.dtb \
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intel-ixp43x-gateworks-gw2358.dtb \
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intel-ixp42x-netgear-wg302v2.dtb
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intel-ixp42x-netgear-wg302v2.dtb \
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intel-ixp42x-arcom-vulcan.dtb
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dtb-$(CONFIG_ARCH_KEYSTONE) += \
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keystone-k2hk-evm.dtb \
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keystone-k2l-evm.dtb \
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167
arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
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167
arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
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@@ -0,0 +1,167 @@
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// SPDX-License-Identifier: ISC
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/*
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* Device Tree file for the Arcom/Eurotech Vulcan board.
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* This board is a single board computer in the PC/104 form factor based on
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* IXP425, and was released around 2005. It previously had the name "Mercury".
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*/
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/dts-v1/;
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#include "intel-ixp42x.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Arcom/Eurotech Vulcan";
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compatible = "arcom,vulcan", "intel,ixp42x";
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#address-cells = <1>;
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#size-cells = <1>;
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x4000000>;
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};
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chosen {
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/* CHECKME: using a harddrive at /dev/sda1 as rootfs by default */
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bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait";
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stdout-path = "uart0:115200n8";
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};
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aliases {
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serial0 = &uart0;
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};
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onewire {
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compatible = "w1-gpio";
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gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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};
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soc {
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bus@c4000000 {
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flash@0,0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/*
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* 32 MB of Flash in 0x20000 byte blocks
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* mapped in at CS0 and CS1.
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*
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* The documentation mentions the existence
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* of a 16MB version, which we conveniently
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* ignore. Shout if you own one!
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*/
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reg = <0 0x00000000 0x2000000>;
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/* Expansion bus settings */
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intel,ixp4xx-eb-t3 = <3>;
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intel,ixp4xx-eb-byte-access-on-halfword = <1>;
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intel,ixp4xx-eb-write-enable = <1>;
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partitions {
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compatible = "redboot-fis";
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fis-index-block = <0x1ff>;
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};
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};
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sram@2,0 {
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/* 256 KB SDRAM memory at CS2 */
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compatible = "shared-dma-pool";
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device_type = "memory";
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reg = <2 0x00000000 0x40000>;
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no-map;
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/* Expansion bus settings */
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intel,ixp4xx-eb-t3 = <1>;
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intel,ixp4xx-eb-t4 = <2>;
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intel,ixp4xx-eb-ahb-split-transfers = <1>;
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intel,ixp4xx-eb-write-enable = <1>;
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intel,ixp4xx-eb-byte-access = <1>;
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};
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serial@3,0 {
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/*
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* 8250-compatible Exar XR16L2551 2 x UART
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*
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* CHECKME: if special tweaks are needed, then fix the
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* operating system to handle it.
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*/
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compatible = "exar,xr16l2551", "ns8250";
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reg = <3 0x00000000 0x10>;
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interrupt-parent = <&gpio0>;
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interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
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clock-frequency = <1843200>;
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/* Expansion bus settings */
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intel,ixp4xx-eb-t3 = <3>;
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intel,ixp4xx-eb-cycle-type = <1>; /* Motorola cycles */
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intel,ixp4xx-eb-write-enable = <1>;
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intel,ixp4xx-eb-byte-access = <1>;
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};
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gpio1: gpio@4,0 {
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/*
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* MMIO GPIO in one byte
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*/
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compatible = "arcom,vulcan-gpio";
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reg = <4 0x00000000 0x1>;
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/* Expansion bus settings */
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intel,ixp4xx-eb-write-enable = <1>;
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intel,ixp4xx-eb-byte-access = <1>;
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};
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watchdog@5,0 {
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compatible = "maxim,max6369";
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reg = <5 0x00000000 0x1>;
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/* Expansion bus settings */
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intel,ixp4xx-eb-write-enable = <1>;
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intel,ixp4xx-eb-byte-access = <1>;
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};
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};
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pci@c0000000 {
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status = "ok";
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/*
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* Taken from Vulcan PCI boardfile.
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*
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* We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt
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* per slot. This interrupt is shared (OR:ed) by all four pins.
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*/
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interrupt-map =
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/* IDSEL 1 */
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<0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */
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<0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 2 */
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<0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 2 */
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<0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 2 */
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/* IDSEL 2 */
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<0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 3 */
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<0x1000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 3 */
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<0x1000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 3 */
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<0x1000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 3 */
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};
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/* EthB */
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ethernet@c8009000 {
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status = "ok";
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queue-rx = <&qmgr 3>;
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queue-txready = <&qmgr 20>;
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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/* EthC */
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ethernet@c800a000 {
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status = "ok";
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queue-rx = <&qmgr 4>;
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queue-txready = <&qmgr 21>;
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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};
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};
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