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staging: comedi: ni_tio: tidy up Gi_Mode_Bits
Convert this enum into defines and rename the CamelCase symbols. For aesthetics, move the new defines so they are associated with the register define. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
c2c6c288f9
commit
36d80f4a54
@@ -441,18 +441,18 @@ static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
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NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
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NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
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mode_reg_mask = mode_reg_direct_mask | Gi_Reload_Source_Switching_Bit;
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mode_reg_mask = mode_reg_direct_mask | GI_RELOAD_SRC_SWITCHING;
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mode_reg_values = mode & mode_reg_direct_mask;
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switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
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case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
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break;
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case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
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mode_reg_values |= Gi_Reload_Source_Switching_Bit;
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mode_reg_values |= GI_RELOAD_SRC_SWITCHING;
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break;
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case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
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input_select_bits |= GI_GATE_SEL_LOAD_SRC;
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mode_reg_mask |= Gi_Gating_Mode_Mask;
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mode_reg_values |= Gi_Level_Gating_Bits;
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mode_reg_mask |= GI_GATING_MODE_MASK;
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mode_reg_values |= GI_LEVEL_GATING;
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break;
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default:
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break;
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@@ -907,18 +907,18 @@ int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
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case 0:
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if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
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ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
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Gi_Gating_Mode_Mask,
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Gi_Gating_Disabled_Bits);
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GI_GATING_MODE_MASK,
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GI_GATING_DISABLED);
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return 0;
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}
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if (gate_source & CR_INVERT)
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mode |= Gi_Gate_Polarity_Bit;
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mode |= GI_GATE_POL_INVERT;
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if (gate_source & CR_EDGE)
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mode |= Gi_Rising_Edge_Gating_Bits;
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mode |= GI_RISING_EDGE_GATING;
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else
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mode |= Gi_Level_Gating_Bits;
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mode |= GI_LEVEL_GATING;
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ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
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Gi_Gate_Polarity_Bit | Gi_Gating_Mode_Mask,
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GI_GATE_POL_INVERT | GI_GATING_MODE_MASK,
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mode);
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switch (counter_dev->variant) {
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case ni_gpct_variant_e_series:
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@@ -1132,7 +1132,7 @@ static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
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switch (gate_index) {
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case 0:
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if ((mode & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits) {
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if ((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED) {
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*gate_source = NI_GPCT_DISABLED_GATE_SELECT;
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return 0;
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}
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@@ -1150,13 +1150,13 @@ static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
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*gate_source = ni_660x_gate_to_generic_gate(gate);
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break;
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}
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if (mode & Gi_Gate_Polarity_Bit)
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if (mode & GI_GATE_POL_INVERT)
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*gate_source |= CR_INVERT;
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if ((mode & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
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if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
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*gate_source |= CR_EDGE;
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break;
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case 1:
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if ((mode & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits ||
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if ((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED ||
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!(counter_dev->regs[gate2_reg] & Gi_Second_Gate_Mode_Bit)) {
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*gate_source = NI_GPCT_DISABLED_GATE_SELECT;
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return 0;
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@@ -1179,7 +1179,7 @@ static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
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if (counter_dev->regs[gate2_reg] & Gi_Second_Gate_Polarity_Bit)
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*gate_source |= CR_INVERT;
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/* second gate can't have edge/level mode set independently */
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if ((mode & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
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if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
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*gate_source |= CR_EDGE;
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break;
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default:
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@@ -42,6 +42,35 @@
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#define NITIO_HW_SAVE_REG(x) (NITIO_G0_HW_SAVE + (x))
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#define NITIO_SW_SAVE_REG(x) (NITIO_G0_SW_SAVE + (x))
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#define NITIO_MODE_REG(x) (NITIO_G0_MODE + (x))
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#define GI_GATING_DISABLED (0 << 0)
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#define GI_LEVEL_GATING (1 << 0)
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#define GI_RISING_EDGE_GATING (2 << 0)
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#define GI_FALLING_EDGE_GATING (3 << 0)
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#define GI_GATING_MODE_MASK (3 << 0)
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#define GI_GATE_ON_BOTH_EDGES (1 << 2)
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#define GI_EDGE_GATE_STARTS_STOPS (0 << 3)
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#define GI_EDGE_GATE_STOPS_STARTS (1 << 3)
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#define GI_EDGE_GATE_STARTS (2 << 3)
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#define GI_EDGE_GATE_NO_STARTS_OR_STOPS (3 << 3)
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#define GI_EDGE_GATE_MODE_MASK (3 << 3)
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#define GI_STOP_ON_GATE (0 << 5)
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#define GI_STOP_ON_GATE_OR_TC (1 << 5)
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#define GI_STOP_ON_GATE_OR_SECOND_TC (2 << 5)
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#define GI_STOP_MODE_MASK (3 << 5)
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#define GI_LOAD_SRC_SEL (1 << 7)
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#define GI_OUTPUT_TC_PULSE (1 << 8)
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#define GI_OUTPUT_TC_TOGGLE (2 << 8)
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#define GI_OUTPUT_TC_OR_GATE_TOGGLE (3 << 8)
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#define GI_OUTPUT_MODE_MASK (3 << 8)
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#define GI_NO_HARDWARE_DISARM (0 << 10)
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#define GI_DISARM_AT_TC (1 << 10)
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#define GI_DISARM_AT_GATE (2 << 10)
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#define GI_DISARM_AT_TC_OR_GATE (3 << 10)
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#define GI_COUNTING_ONCE_MASK (3 << 10)
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#define GI_LOADING_ON_TC (1 << 12)
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#define GI_GATE_POL_INVERT (1 << 13)
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#define GI_LOADING_ON_GATE (1 << 14)
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#define GI_RELOAD_SRC_SWITCHING (1 << 15)
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#define NITIO_LOADA_REG(x) (NITIO_G0_LOADA + (x))
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#define NITIO_LOADB_REG(x) (NITIO_G0_LOADB + (x))
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#define NITIO_INPUT_SEL_REG(x) (NITIO_G0_INPUT_SEL + (x))
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@@ -91,39 +120,6 @@
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#define NITIO_STATUS_REG(x) (NITIO_G0_STATUS + (x))
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#define NITIO_INT_ENA_REG(x) (NITIO_G0_INT_ENA + (x))
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enum Gi_Mode_Bits {
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Gi_Gating_Mode_Mask = 0x3,
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Gi_Gating_Disabled_Bits = 0x0,
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Gi_Level_Gating_Bits = 0x1,
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Gi_Rising_Edge_Gating_Bits = 0x2,
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Gi_Falling_Edge_Gating_Bits = 0x3,
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Gi_Gate_On_Both_Edges_Bit = 0x4, /* used in conjunction with
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* rising edge gating mode */
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Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
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Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
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Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
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Gi_Edge_Gate_Starts_Bits = 0x10,
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Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
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Gi_Stop_Mode_Mask = 0x60,
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Gi_Stop_on_Gate_Bits = 0x00,
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Gi_Stop_on_Gate_or_TC_Bits = 0x20,
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Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
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Gi_Load_Source_Select_Bit = 0x80,
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Gi_Output_Mode_Mask = 0x300,
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Gi_Output_TC_Pulse_Bits = 0x100,
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Gi_Output_TC_Toggle_Bits = 0x200,
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Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
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Gi_Counting_Once_Mask = 0xc00,
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Gi_No_Hardware_Disarm_Bits = 0x000,
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Gi_Disarm_at_TC_Bits = 0x400,
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Gi_Disarm_at_Gate_Bits = 0x800,
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Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
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Gi_Loading_On_TC_Bit = 0x1000,
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Gi_Gate_Polarity_Bit = 0x2000,
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Gi_Loading_On_Gate_Bit = 0x4000,
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Gi_Reload_Source_Switching_Bit = 0x8000
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};
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#define Gi_Second_Gate_Select_Shift 7
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/*FIXME: m-series has a second gate subselect bit */
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/*FIXME: m-series second gate sources are undocumented (by NI)*/
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@@ -403,7 +403,7 @@ void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter, int *gate_error,
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if (ack)
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write_register(counter, ack, NITIO_INT_ACK_REG(cidx));
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if (ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)) &
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Gi_Loading_On_Gate_Bit) {
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GI_LOADING_ON_GATE) {
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if (gxx_status & Gi_Stale_Data_Bit(cidx)) {
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if (stale_data)
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*stale_data = 1;
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