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drm/amdgpu: program GRBM_MCM_ADDR for non-AID0 GRBM

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Otherwise the EOP interrupt on non-AID0 cannot route to IH0.

Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Le Ma
2022-04-20 23:25:48 +08:00
committed by Alex Deucher
parent feb36dd014
commit 36be0181ea
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
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@@ -184,7 +184,10 @@ static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev)
static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)
{
int i;
for (i = 2; i < adev->gfx.num_xcd; i++)
WREG32_SOC15(GC, i, regGRBM_MCM_ADDR, 0x4);
}
static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,