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drm/i915/cx0: Zero Cx0 PLL state before compute and HW readout

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Ensure Cx0 pll state is initialized to zero before any computation or HW
readouts, to prevent leaving some parameter in the state uninitialized
in the actual compute/HW readout functions later.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-14-mika.kahola@intel.com
This commit is contained in:
Imre Deak
2025-11-17 12:45:43 +02:00
committed by Mika Kahola
parent 538187f17a
commit 36a3efb32e
1 changed files with 3 additions and 1 deletions
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4
drivers/gpu/drm/i915/display/intel_cx0_phy.c
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@@ -2679,6 +2679,8 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state->dpll_hw_state));
if (intel_encoder_is_c10phy(encoder))
return intel_c10pll_calc_state(crtc_state, encoder);
return intel_c20pll_calc_state(crtc_state, encoder);
@@ -3612,7 +3614,7 @@ static void intel_c10pll_state_verify(const struct intel_crtc_state *state,
void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_cx0pll_state *pll_state)
{
pll_state->use_c10 = false;
memset(pll_state, 0, sizeof(*pll_state));
pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
if (pll_state->tbt_mode)