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ath9k: Fix chainmask selection for AR9462
Force chain 1 to be used for CCK rates since the target power table stored in EEPROM is too high to transmit with both chains. This is needed to avoid regulatory violation. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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committed by
John W. Linville
parent
8b4509f642
commit
365d2ebcab
@@ -173,6 +173,8 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
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#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
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#define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
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#define ATH_TX_COMPLETE_POLL_INT 1000
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enum ATH_AGGR_STATUS {
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@@ -1820,10 +1820,14 @@ u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
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{
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struct ath_hw *ah = sc->sc_ah;
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struct ath9k_channel *curchan = ah->curchan;
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if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
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(curchan->channelFlags & CHANNEL_5GHZ) &&
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(chainmask == 0x7) && (rate < 0x90))
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return 0x3;
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else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
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IS_CCK_RATE(rate))
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return 0x2;
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else
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return chainmask;
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}
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