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dt-bindings: mmc: samsung,exynos-dw-mshc: convert to dtschema
Convert the Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile Storage Host Controller to DT schema. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220605163710.144210-4-krzysztof.kozlowski@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Krzysztof Kozlowski
committed by
Ulf Hansson
Ulf Hansson
parent
e5f7a3c64c
commit
354c6d33dd
@@ -1,94 +0,0 @@
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* Samsung Exynos specific extensions to the Synopsys Designware Mobile
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Storage Host Controller
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The Synopsys designware mobile storage host controller is used to interface
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a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
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differences between the core Synopsys dw mshc controller properties described
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by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
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extensions to the Synopsys Designware Mobile Storage Host Controller.
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Required Properties:
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* compatible: should be
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- "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
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specific extensions.
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- "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
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specific extensions.
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- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
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specific extensions.
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- "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
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specific extensions.
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- "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
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specific extensions.
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- "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
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specific extensions having an SMU.
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- "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific
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extensions.
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* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
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unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
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ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
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* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
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in transmit mode and CIU clock phase shift value in receive mode for single
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data rate mode operation. Refer notes below for the order of the cells and the
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valid values.
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* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
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in transmit mode and CIU clock phase shift value in receive mode for double
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data rate mode operation. Refer notes below for the order of the cells and the
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valid values.
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* samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
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shift value for hs400 mode operation.
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Notes for the sdr-timing and ddr-timing values:
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The order of the cells should be
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- First Cell: CIU clock phase shift value for tx mode.
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- Second Cell: CIU clock phase shift value for rx mode.
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Valid values for SDR and DDR CIU clock timing for Exynos5250:
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- valid value for tx phase shift and rx phase shift is 0 to 7.
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- when CIU clock divider value is set to 3, all possible 8 phase shift
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values can be used.
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- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
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phase shift clocks should be 0.
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* samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
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(Latency value for delay line in Read path)
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Required properties for a slot (Deprecated - Recommend to use one slot per host):
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* gpios: specifies a list of gpios used for command, clock and data bus. The
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first gpio is the command line and the second gpio is the clock line. The
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rest of the gpios (depending on the bus-width property) are the data lines in
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no particular order. The format of the gpio specifier depends on the gpio
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controller.
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(Deprecated - Refer to Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt)
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Example:
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The MSHC controller node can be split into two portions, SoC specific and
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board specific portions as listed below.
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dwmmc0@12200000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12200000 0x1000>;
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interrupts = <0 75 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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dwmmc0@12200000 {
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cap-mmc-highspeed;
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cap-sd-highspeed;
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broken-cd;
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fifo-depth = <0x80>;
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card-detect-delay = <200>;
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samsung,dw-mshc-ciu-div = <3>;
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samsung,dw-mshc-sdr-timing = <2 3>;
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samsung,dw-mshc-ddr-timing = <1 2>;
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samsung,dw-mshc-hs400-timing = <0 2>;
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samsung,read-strobe-delay = <90>;
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bus-width = <8>;
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};
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@@ -0,0 +1,159 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title:
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Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile
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Storage Host Controller
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maintainers:
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- Jaehoon Chung <jh80.chung@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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properties:
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compatible:
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enum:
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- samsung,exynos4210-dw-mshc
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- samsung,exynos4412-dw-mshc
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- samsung,exynos5250-dw-mshc
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- samsung,exynos5420-dw-mshc
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- samsung,exynos7-dw-mshc
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- samsung,exynos7-dw-mshc-smu
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- axis,artpec8-dw-mshc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 2
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description:
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Handle to "biu" and "ciu" clocks for the
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bus interface unit clock and the card interface unit clock.
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clock-names:
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items:
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- const: biu
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- const: ciu
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samsung,dw-mshc-ciu-div:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 7
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description:
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The divider value for the card interface unit (ciu) clock.
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samsung,dw-mshc-ddr-timing:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: CIU clock phase shift value for tx mode
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minimum: 0
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maximum: 7
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- description: CIU clock phase shift value for rx mode
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minimum: 0
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maximum: 7
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description:
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The value of CUI clock phase shift value in transmit mode and CIU clock
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phase shift value in receive mode for double data rate mode operation.
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See also samsung,dw-mshc-hs400-timing property.
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samsung,dw-mshc-hs400-timing:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: CIU clock phase shift value for tx mode
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minimum: 0
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maximum: 7
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- description: CIU clock phase shift value for rx mode
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minimum: 0
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maximum: 7
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description: |
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The value of CIU TX and RX clock phase shift value for HS400 mode
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operation.
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Valid values for SDR and DDR CIU clock timing::
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- valid value for tx phase shift and rx phase shift is 0 to 7.
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- when CIU clock divider value is set to 3, all possible 8 phase shift
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values can be used.
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- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
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phase shift clocks should be 0.
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If missing, values from samsung,dw-mshc-ddr-timing property are used.
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samsung,dw-mshc-sdr-timing:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: CIU clock phase shift value for tx mode
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minimum: 0
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maximum: 7
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- description: CIU clock phase shift value for rx mode
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minimum: 0
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maximum: 7
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description:
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The value of CIU clock phase shift value in transmit mode and CIU clock
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phase shift value in receive mode for single data rate mode operation.
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See also samsung,dw-mshc-hs400-timing property.
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samsung,read-strobe-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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RCLK (Data strobe) delay to control HS400 mode (Latency value for delay
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line in Read path). If missing, default from hardware is used.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- samsung,dw-mshc-ddr-timing
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- samsung,dw-mshc-sdr-timing
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allOf:
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- $ref: "synopsys-dw-mshc-common.yaml#"
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynos5250-dw-mshc
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- samsung,exynos5420-dw-mshc
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- samsung,exynos7-dw-mshc
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- samsung,exynos7-dw-mshc-smu
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- axis,artpec8-dw-mshc
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then:
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required:
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- samsung,dw-mshc-ciu-div
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos5420.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mmc@12220000 {
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compatible = "samsung,exynos5420-dw-mshc";
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12220000 0x1000>;
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clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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card-detect-delay = <200>;
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samsung,dw-mshc-ciu-div = <3>;
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samsung,dw-mshc-sdr-timing = <0 4>;
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samsung,dw-mshc-ddr-timing = <0 2>;
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pinctrl-names = "default";
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pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
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bus-width = <4>;
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cap-sd-highspeed;
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max-frequency = <200000000>;
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vmmc-supply = <&ldo19_reg>;
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vqmmc-supply = <&ldo13_reg>;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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};
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