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arm64: dts: rockchip: enable pcie on Sige5

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The ArmSoM Sige5 board exposes PCIe controller 0 on its M.2 slot on the
bottom of the board. Enable the necessary nodes for it, and also add the
correct pins for both the power enable GPIO and the PCIe reset GPIO.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250414-rk3576-sige5-pcie-v1-1-0e950a96f392@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Nicolas Frattaroli
2025-04-14 20:37:38 +02:00
committed by Heiko Stuebner
parent b022a48d8d
commit 34b69113ab
1 changed files with 23 additions and 0 deletions
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23
arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts
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@@ -117,6 +117,8 @@ vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
vcc_3v3_pcie: regulator-vcc-3v3-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pcie_pwr_en>;
regulator-name = "vcc_3v3_pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -177,6 +179,10 @@ vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 {
};
};
&combphy0_ps {
status = "okay";
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
@@ -634,6 +640,14 @@ rgmii_phy1: phy@1 {
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset>;
reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_pcie>;
status = "okay";
};
&pinctrl {
headphone {
hp_det: hp-det {
@@ -655,6 +669,15 @@ led_rgb_g: led-green-en {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>;
};
pcie_reset: pcie-reset {
rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&sdhci {