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Merge tag 'ixp4xx-dts-arm-soc-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt

Browse Source 
IXP4xx DTS file updates for the v5.15 kernel cycle:

- Fix up some (non-urgent) IRQ flags for the PCI buses.

- Add the second UART to the generic ixp4xx.dtsi

- Make use of the new expansion bus driver in all device
  trees with e.g. flash memory on the expansion bus.

- Adds the CF card slot to the Gateworks GW2358.

- Add new device trees for:
  - Iomega NAS 100D
  - D-Link DSM-G600
  - Netgear WG302v2
  - Arcom Vulcan
  - Gateworks Avila GW2348
  - Intel IXPD425 and siblings
  - Coyote and IXDPG425
  - Linksys WRV54G

* tag 'ixp4xx-dts-arm-soc-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
  ARM: dts: ixp4xx: Add a devicetree for Freecom FSG-3
  ARM: dts: ixp4xx: Add devicetree for Linksys WRV54G
  ARM: dts: ixp4xx: Add device trees for Coyote and IXDPG425
  ARM: dts: ixp4xx: Add Intel IXDP425 etc reference designs
  ARM: dts: ixp4xx: Add CF to GW2358
  ARM: dts: ixp4xx: Add Gateworks Avila GW2348 device tree
  ARM: dts: ixp4xx: Add Arcom Vulcan device tree
  ARM: dts: ixp4xx: Add devicetree for Netgear WG302v2
  ARM: dts: ixp4xx: Use the expansion bus
  ARM: dts: ixp4xx: Add second UART
  ARM: dts: ixp4xx: Add devicetree for D-Link DSM-G600 rev A
  ARM: dts: ixp4xx: Move EPBX100 flash to external bus node
  ARM: dts: ixp4xx: Add devicetree for Iomega NAS 100D
  ARM: dts: ixp4xx: Fix up bad interrupt flags

Link: https://lore.kernel.org/r/CACRpkdY19AvWT--OcmEKbwFue_EcThVs7uZeHkzORten7xj-RA@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2021-08-12 22:50:18 +02:00
parent 57798ff216 f2841e3ab1
commit 34827ffe35
21 changed files with 1784 additions and 92 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
arch/arm/boot/dts/Makefile
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@@ -243,8 +243,20 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += \
integratorcp.dtb
dtb-$(CONFIG_ARCH_IXP4XX) += \
intel-ixp42x-linksys-nslu2.dtb \
intel-ixp42x-linksys-wrv54g.dtb \
intel-ixp42x-freecom-fsg-3.dtb \
intel-ixp42x-welltech-epbx100.dtb \
intel-ixp43x-gateworks-gw2358.dtb
intel-ixp42x-ixdp425.dtb \
intel-ixp43x-kixrp435.dtb \
intel-ixp46x-ixdp465.dtb \
intel-ixp42x-adi-coyote.dtb \
intel-ixp42x-ixdpg425.dtb \
intel-ixp42x-iomega-nas100d.dtb \
intel-ixp42x-dlink-dsm-g600.dtb \
intel-ixp42x-gateworks-gw2348.dtb \
intel-ixp43x-gateworks-gw2358.dtb \
intel-ixp42x-netgear-wg302v2.dtb \
intel-ixp42x-arcom-vulcan.dtb
dtb-$(CONFIG_ARCH_KEYSTONE) += \
keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \

110
arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts Normal file
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@@ -0,0 +1,110 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree file for ADI Engineering Coyote platform.
* Derived from boardfiles written by MontaVista software.
* Ethernet set-up from OpenWrt.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "ADI Engineering Coyote reference design";
compatible = "adieng,coyote", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */
device_type = "memory";
reg = <0x00000000 0x01000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
stdout-path = "uart1:115200n8";
};
aliases {
/* These are switched around */
serial0 = &uart1;
serial1 = &uart0;
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 32 MB of Flash in 128 0x20000 sized blocks
* mapped in at CS0 and CS1
*/
reg = <0 0x00000000 0x2000000>;
/* Configure expansion bus to allow writes */
intel,ixp4xx-eb-write-enable = <1>;
partitions {
compatible = "redboot-fis";
/* CHECKME: guess this is Redboot FIS */
fis-index-block = <0x1ff>;
};
};
};
pci@c0000000 {
status = "ok";
/*
* Taken from Coyote PCI boardfile.
* We have slots (IDSEL) 1 and 2 with one assigned IRQ
* each handling all IRQs.
*/
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */
<0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */
<0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */
<0x0800 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 6 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */
<0x1000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 11 */
<0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */
<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 11 */
};
/* EthB */
ethernet@c8009000 {
status = "ok";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy4: ethernet-phy@4 {
reg = <4>;
};
phy5: ethernet-phy@5 {
reg = <5>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "ok";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy4>;
};
};
};

167
arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts Normal file
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@@ -0,0 +1,167 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Arcom/Eurotech Vulcan board.
* This board is a single board computer in the PC/104 form factor based on
* IXP425, and was released around 2005. It previously had the name "Mercury".
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Arcom/Eurotech Vulcan";
compatible = "arcom,vulcan", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
/* CHECKME: using a harddrive at /dev/sda1 as rootfs by default */
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
onewire {
compatible = "w1-gpio";
gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 32 MB of Flash in 0x20000 byte blocks
* mapped in at CS0 and CS1.
*
* The documentation mentions the existence
* of a 16MB version, which we conveniently
* ignore. Shout if you own one!
*/
reg = <0 0x00000000 0x2000000>;
/* Expansion bus settings */
intel,ixp4xx-eb-t3 = <3>;
intel,ixp4xx-eb-byte-access-on-halfword = <1>;
intel,ixp4xx-eb-write-enable = <1>;
partitions {
compatible = "redboot-fis";
fis-index-block = <0x1ff>;
};
};
sram@2,0 {
/* 256 KB SDRAM memory at CS2 */
compatible = "shared-dma-pool";
device_type = "memory";
reg = <2 0x00000000 0x40000>;
no-map;
/* Expansion bus settings */
intel,ixp4xx-eb-t3 = <1>;
intel,ixp4xx-eb-t4 = <2>;
intel,ixp4xx-eb-ahb-split-transfers = <1>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
};
serial@3,0 {
/*
* 8250-compatible Exar XR16L2551 2 x UART
*
* CHECKME: if special tweaks are needed, then fix the
* operating system to handle it.
*/
compatible = "exar,xr16l2551", "ns8250";
reg = <3 0x00000000 0x10>;
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <1843200>;
/* Expansion bus settings */
intel,ixp4xx-eb-t3 = <3>;
intel,ixp4xx-eb-cycle-type = <1>; /* Motorola cycles */
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
};
gpio1: gpio@4,0 {
/*
* MMIO GPIO in one byte
*/
compatible = "arcom,vulcan-gpio";
reg = <4 0x00000000 0x1>;
/* Expansion bus settings */
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
};
watchdog@5,0 {
compatible = "maxim,max6369";
reg = <5 0x00000000 0x1>;
/* Expansion bus settings */
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
};
};
pci@c0000000 {
status = "ok";
/*
* Taken from Vulcan PCI boardfile.
*
* We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt
* per slot. This interrupt is shared (OR:ed) by all four pins.
*/
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */
<0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 2 */
<0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 2 */
<0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 2 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 3 */
<0x1000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 3 */
<0x1000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 3 */
<0x1000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 3 */
};
/* EthB */
ethernet@c8009000 {
status = "ok";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "ok";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
};
};

145
arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts Normal file
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@@ -0,0 +1,145 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree file for D-Link DSM-G600 revision A based on IXP420
* NOTE: revision B of this device uses PowerPC and is NOT supported by
* this device tree.
*
* Inspired by the boardfile by Rod Whitby, Tower Technologies, Alessandro Zummo
* and Michael Westerhof.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "D-Link DSM-G600 rev A";
compatible = "dlink,dsm-g600-a", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 64 MB SDRAM */
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
leds {
compatible = "gpio-leds";
led-power {
label = "dsmg600:green:power";
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-wlan {
label = "dsmg600:green:wlan";
/* CHECKME: flagged as active low in the old board file */
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
default-state = "on";
/* We don't have WLAN trigger in the kernel (yet) */
linux,default-trigger = "netdev";
};
};
gpio_keys {
compatible = "gpio-keys";
button-reset {
wakeup-source;
linux,code = <KEY_ESC>;
label = "reset";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
};
};
gpio_keys_polled {
compatible = "gpio-keys-polled";
/*
* According to the board file this key cannot handle interrupts and
* need to be polled. Investigate if this is really the case or if
* this can be moved adjacent to the ordinary gpio-keys above.
*/
button-power {
wakeup-source;
linux,code = <KEY_POWER>;
label = "power";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
};
};
i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
timeout-ms = <5000>;
};
soc {
bus@c4000000 {
/* The first 16MB region at CS0 on the expansion bus */
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 16 MB of Flash in 128 0x20000 sized blocks
* mapped in at CS0.
*/
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";
/*
* A boot log says the directory is at 0xfe0000
* 0x7f * 0x20000 = 0xfe0000
*/
fis-index-block = <0x7f>;
};
};
};
pci@c0000000 {
status = "ok";
/*
* Taken from DSM-G600 PCI boardfile (dsmg600-pci.c)
* We have slots (IDSEL) 1, 2, 3, 4 and pins 1, 2 and 3.
* Only slot 3 have three IRQs.
*/
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT E on slot 1 is irq 7 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */
/* IDSEL 3 */
<0x1800 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 10 */
<0x1800 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 9 */
<0x1800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 8 */
/* IDSEL 4 */
<0x2000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT F on slot 4 is irq 6 */
};
};
};

158
arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts Normal file
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@@ -0,0 +1,158 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Freecom FSG-3 router.
* This machine is based on IXP425.
* This device tree is inspired by the board file by Rod Whitby.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Freecom FSG-3";
compatible = "freecom,fsg-3", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 64 MB memory */
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
/* Boot from the first partition on the hard drive */
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
gpio_keys {
compatible = "gpio-keys";
button-sync {
wakeup-source;
/* Closest approximation of what the key should do */
linux,code = <KEY_CONNECT>;
label = "sync";
gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
};
button-reset {
wakeup-source;
linux,code = <KEY_ESC>;
label = "reset";
gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
};
button-usb {
wakeup-source;
/* Unplug USB, closest approximation of what the key should do */
linux,code = <KEY_EJECTCD>;
label = "usb";
gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
};
};
i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
hwmon@28 {
/*
* Temperature sensor and fan control chip.
*
* TODO: create a proper device tree binding for
* the sensor and temperature zone and create a
* zone with fan control.
*/
compatible = "winbond,w83781d";
reg = <0x28>;
};
rtc@6f {
compatible = "isil,isl1208";
reg = <0x6f>;
};
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 4 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x400000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x3e0000 */
fis-index-block = <0x1f>;
};
};
};
pci@c0000000 {
status = "ok";
/*
* Written based on the FSG-3 PCI boardfile.
* We have slots 12, 13 & 14 (IDSEL) with one IRQ each.
*/
interrupt-map =
/* IDSEL 12 */
<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
<0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
<0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */
<0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */
/* IDSEL 13 */
<0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */
<0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */
<0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */
<0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */
/* IDSEL 14 */
<0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */
<0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */
<0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */
<0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */
};
/* EthB */
ethernet@c8009000 {
status = "ok";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy4: ethernet-phy@4 {
reg = <4>;
};
phy5: ethernet-phy@5 {
reg = <5>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "ok";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy4>;
};
};
};

172
arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts Normal file
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@@ -0,0 +1,172 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Gateworks Avila GW2348 board.
* This machine is based on IXP425.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Gateworks Avila GW2348";
compatible = "gateworks,gw2348", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
leds {
compatible = "gpio-leds";
led-user {
label = "gw2348:green:user";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
};
i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
hwmon@28 {
compatible = "adi,ad7418";
reg = <0x28>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
eeprom@51 {
compatible = "atmel,24c08";
reg = <0x51>;
pagesize = <16>;
size = <1024>;
read-only;
};
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 16 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x0fe0000 */
fis-index-block = <0x7f>;
};
};
ide@1,0 {
compatible = "intel,ixp4xx-compact-flash";
/*
* Set up expansion bus config to a really slow timing.
* The CF driver will dynamically reconfigure these timings
* depending on selected PIO mode (0-4).
*/
intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
intel,ixp4xx-eb-byte-access-on-halfword = <1>;
intel,ixp4xx-eb-mux-address-and-data = <0>;
intel,ixp4xx-eb-ahb-split-transfers = <0>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
/* First register set is CMD second is CTL (notice it uses CS2) */
reg = <1 0x00000000 0x1000000>, <2 0x00000000 0x1000000>;
interrupt-parent = <&gpio0>;
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
};
/*
* FIXME: Latch LEDs or extra UARTs at CS4
*/
};
pci@c0000000 {
status = "ok";
/*
* Taken from Avila PCI boardfile.
*
* We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
*/
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
<0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
<0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
<0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
/* IDSEL 3 */
<0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
<0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
/* IDSEL 4 */
<0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
<0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
};
/* EthB */
ethernet@c8009000 {
status = "ok";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "ok";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
};
};

146
arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts Normal file
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@@ -0,0 +1,146 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree file for Iomega NAS 100D
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Iomega NAS 100D";
compatible = "iom,nas-100d", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 64 MB SDRAM */
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
leds {
compatible = "gpio-leds";
led-wlan {
label = "nas100d:red:wlan";
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
default-state = "on";
/* We don't have WLAN trigger in the kernel (yet) */
linux,default-trigger = "netdev";
};
led-disk {
label = "nas100d:red:disk";
gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "disk-activity";
};
led-power {
label = "nas100d:red:power";
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
};
gpio_keys {
compatible = "gpio-keys";
button-power {
wakeup-source;
linux,code = <KEY_POWER>;
label = "power";
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
};
button-reset {
wakeup-source;
linux,code = <KEY_ESC>;
label = "reset";
gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
};
};
i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
timeout-ms = <5000>;
};
soc {
bus@c4000000 {
/* The first 16MB region at CS0 on the expansion bus */
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 8 MB of Flash in 0x20000 byte blocks
* mapped in at CS0.
*/
reg = <0 0x00000000 0x800000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x7e0000 */
fis-index-block = <0x3f>;
};
};
};
pci@c0000000 {
status = "ok";
/*
* Taken from NAS 100D PCI boardfile (nas100d-pci.c)
* We have slots (IDSEL) 1, 2 and 3 and pins 1, 2 and 3.
*/
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
/* IDSEL 3 */
<0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
<0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
<0x1800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 3 is irq 7 */
};
ethernet@c8009000 {
status = "ok";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
};
};

72
arch/arm/boot/dts/intel-ixp42x-ixdp425.dts Normal file
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@@ -0,0 +1,72 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Intel IXDP425 also known as IXCDP1100 Control Plane
* processor reference design.
*
* This platform has the codename "Richfield".
*
* This machine is based on a 533 MHz IXP425.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include "intel-ixp4xx-reference-design.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Intel IXDP425/IXCDP1100 Richfield Reference Design";
compatible = "intel,ixdp425", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 16 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x0fe0000 */
fis-index-block = <0x7f>;
};
};
};
/* EthB */
ethernet@c8009000 {
status = "ok";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "ok";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
};
};

125
arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts Normal file
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@@ -0,0 +1,125 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Intel IXDPG425 reference design.
* Derived from boardfiles written by MontaVista software.
* Ethernet set-up from OpenWrt.
*
* The device has 4 x FXS RJ11 ports for analog phones for
* internet telephony. (Not supported yet.)
*
* The device has 9 status LEDs we do not support yet.
*
* This device is very similar to ADI engingeering Coyote.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Intel IXDPG425 reference design";
compatible = "intel,ixdpg425", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 32 MB SDRAM */
device_type = "memory";
reg = <0x00000000 0x02000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* CHECKME: the product brief says 16MB in a flash
* socket.
*/
reg = <0 0x00000000 0x1000000>;
/* Configure expansion bus to allow writes */
intel,ixp4xx-eb-write-enable = <1>;
partitions {
compatible = "redboot-fis";
/* CHECKME: guess this is Redboot FIS */
fis-index-block = <0x7f>;
};
};
};
pci@c0000000 {
status = "ok";
/*
* Taken from IXDPG425 PCI boardfile.
* We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ
* for 12 & 13 and one for 14.
*/
interrupt-map =
/* IDSEL 12 */
<0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */
<0x6000 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 7 */
<0x6000 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 7 */
<0x6000 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 7 */
/* IDSEL 13 */
<0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */
<0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */
<0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */
<0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */
/* IDSEL 14 */
<0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */
<0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */
<0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */
<0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */
};
/*
* CHECKME: this ethernet setup seems dubious. Photos of the board shows some kind
* of Realtek DSA switch on the board.
*/
/* EthB */
ethernet@c8009000 {
status = "ok";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy4: ethernet-phy@4 {
reg = <4>;
};
phy5: ethernet-phy@5 {
reg = <5>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "ok";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy4>;
};
};
};

30
arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
View File

@@ -96,16 +96,16 @@ gpio-beeper {
};
soc {
bus@50000000 {
bus@c4000000 {
/* The first 16MB region at CS0 on the expansion bus */
flash@0 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 8 MB of Flash in 0x20000 byte blocks
* mapped in at CS0.
*/
reg = <0x00000000 0x800000>;
reg = <0 0x00000000 0x800000>;
partitions {
compatible = "redboot-fis";
@@ -124,20 +124,20 @@ pci@c0000000 {
*/
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
<0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
<0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
<0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
<0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
<0x1000 0 0 3 &gpio0 11 3>, /* INT C on slot 2 is irq 11 */
<0x1000 0 0 4 &gpio0 8 3>, /* INT D on slot 2 is irq 8 */
<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
<0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
<0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */
<0x1000 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 8 */
/* IDSEL 3 */
<0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
<0x1800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
<0x1800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
<0x1800 0 0 4 &gpio0 8 3>; /* INT D on slot 3 is irq 8 */
<0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
<0x1800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
<0x1800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
<0x1800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 8 */
};
ethernet@c8009000 {

173
arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts Normal file
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@@ -0,0 +1,173 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Linksys WRV54G router
* Also known as Gemtek GTWX5715
* Based on a board file by George T. Joseph and other patches.
* This machine is based on IXP425.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Linksys WRV54G / Gemtek GTWX5715";
compatible = "linksys,wrv54g", "gemtek,gtwx5715", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 32 MB memory */
device_type = "memory";
reg = <0x00000000 0x2000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "uart1:115200n8";
};
aliases {
/* UART2 is the primary console */
serial0 = &uart1;
serial1 = &uart0;
};
/* There is an unpopulated LED slot (3) connected to GPIO 8 */
leds {
compatible = "gpio-leds";
led-power {
label = "wrv54g:yellow:power";
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-wireless {
label = "wrv54g:yellow:wireless";
gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led-internet {
label = "wrv54g:yellow:internet";
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led-dmz {
label = "wrv54g:green:dmz";
gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
default-state = "on";
};
};
/* This set-up comes from an OpenWrt patch */
spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
switch@0 {
compatible = "micrel,ks8995";
reg = <0>;
spi-max-frequency = <50000000>;
};
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 8 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x00800000>;
partitions {
compatible = "fixed-partitions";
/*
* Partition info from a boot log
* CHECKME: not using redboot? FIS index 0x3f @7e00000?
*/
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
reg = <0x0 0x140000>;
read-only;
};
partition@140000 {
label = "linux";
reg = <0x140000 0x100000>;
read-only;
};
partition@240000 {
label = "root";
reg = <0x240000 0x480000>;
read-write;
};
};
};
};
pci@c0000000 {
status = "ok";
/*
* We have up to 2 slots (IDSEL) with 2 swizzled IRQs.
* Derived from the GTWX5715 PCI boardfile.
*/
interrupt-map =
/* IDSEL 0 */
<0x0000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 0 is irq 10 */
<0x0000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 0 is irq 11 */
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 1 is irq 10 */
};
/*
* EthB - connected to the KS8995 switch ports 1-4
* FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to
* all four switch ports, also using an out of tree multiphy patch.
* Do we need a new binding and property for this?
*/
ethernet@c8009000 {
status = "ok";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy4>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* Should be ports 1-4 on the KS8995 switch */
phy4: ethernet-phy@4 {
reg = <4>;
};
/* Should be port 5 on the KS8995 switch */
phy5: ethernet-phy@5 {
reg = <5>;
};
};
};
/* EthC - connected to KS8995 switch port 5 */
ethernet@c800a000 {
status = "ok";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
};

95
arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts Normal file
View File

@@ -0,0 +1,95 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree file for Netgear WG302v2 based on IXP422BB
* Derived from boardfiles written by Imre Kaloz
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Netgear WG302 v2";
compatible = "netgear,wg302v2", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 16 MB SDRAM according to OpenWrt database */
device_type = "memory";
reg = <0x00000000 0x01000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
stdout-path = "uart1:115200n8";
};
aliases {
/* These are switched around */
serial0 = &uart1;
serial1 = &uart0;
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 32 MB of Flash in 128 0x20000 sized blocks
* mapped in at CS0 and CS1
*/
reg = <0 0x00000000 0x2000000>;
/* Configure expansion bus to allow writes */
intel,ixp4xx-eb-write-enable = <1>;
partitions {
compatible = "redboot-fis";
/* CHECKME: guess this is Redboot FIS */
fis-index-block = <0xff>;
};
};
};
pci@c0000000 {
status = "ok";
/*
* Taken from WG302 v2 PCI boardfile (wg302v2-pci.c)
* We have slots (IDSEL) 1 and 2 with one assigned IRQ
* each handling all IRQs.
*/
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */
<0x0800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 8 */
<0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */
<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 9 */
<0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
<0x1000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 9 */
<0x1000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 9 */
};
ethernet@c8009000 {
status = "ok";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy8>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy8: ethernet-phy@8 {
reg = <8>;
};
};
};
};
};

84
arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts
View File

@@ -28,48 +28,52 @@ aliases {
serial0 = &uart0;
};
flash@50000000 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 16 MB of Flash
*/
reg = <0x50000000 0x1000000>;
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 16 MB of Flash
*/
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "RedBoot";
reg = <0x00000000 0x00080000>;
read-only;
};
partition@80000 {
label = "zImage";
reg = <0x00080000 0x00100000>;
read-only;
};
partition@180000 {
label = "ramdisk";
reg = <0x00180000 0x00300000>;
read-only;
};
partition@480000 {
label = "User";
reg = <0x00480000 0x00b60000>;
read-only;
};
partition@fe0000 {
label = "FIS directory";
reg = <0x00fe0000 0x001f000>;
read-only;
};
partition@fff000 {
label = "RedBoot config";
reg = <0x00fff000 0x0001000>;
read-only;
partition@0 {
label = "RedBoot";
reg = <0x00000000 0x00080000>;
read-only;
};
partition@80000 {
label = "zImage";
reg = <0x00080000 0x00100000>;
read-only;
};
partition@180000 {
label = "ramdisk";
reg = <0x00180000 0x00300000>;
read-only;
};
partition@480000 {
label = "User";
reg = <0x00480000 0x00b60000>;
read-only;
};
partition@fe0000 {
label = "FIS directory";
reg = <0x00fe0000 0x001f000>;
read-only;
};
partition@fff000 {
label = "RedBoot config";
reg = <0x00fff000 0x0001000>;
read-only;
};
};
};
};
};

5
arch/arm/boot/dts/intel-ixp42x.dtsi
View File

@@ -7,6 +7,11 @@
/ {
soc {
bus@c4000000 {
compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
reg = <0xc4000000 0x28>;
};
pci@c0000000 {
compatible = "intel,ixp42x-pci";
};

81
arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
View File

@@ -77,15 +77,17 @@ pld1: pld@57 {
};
soc {
bus@50000000 {
flash@0 {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/*
* 32 MB of Flash in 0x20000 byte blocks
* mapped in at CS0.
* mapped in at CS0 and CS1
*/
reg = <0x00000000 0x2000000>;
reg = <0 0x00000000 0x2000000>;
partitions {
compatible = "redboot-fis";
@@ -93,6 +95,29 @@ partitions {
fis-index-block = <0xff>;
};
};
ide@3,0 {
compatible = "intel,ixp4xx-compact-flash";
/*
* Set up expansion bus config to a really slow timing.
* The CF driver will dynamically reconfigure these timings
* depending on selected PIO mode (0-4).
*/
intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
intel,ixp4xx-eb-byte-access-on-halfword = <1>;
intel,ixp4xx-eb-mux-address-and-data = <0>;
intel,ixp4xx-eb-ahb-split-transfers = <0>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
/* First register set is CMD second is CTL */
reg = <3 0xe00000 0x40000>, <3 0xe40000 0x40000>;
interrupt-parent = <&gpio0>;
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
};
};
pci@c0000000 {
@@ -108,35 +133,35 @@ pci@c0000000 {
*/
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
<0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
<0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
<0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
<0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
<0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */
<0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
<0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
<0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
/* IDSEL 3 */
<0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
<0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */
<0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
<0x1800 0 0 4 &gpio0 10 3>, /* INT D on slot 3 is irq 10 */
<0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
<0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
/* IDSEL 4 */
<0x2000 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */
<0x2000 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
<0x2000 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
<0x2000 0 0 4 &gpio0 9 3>, /* INT D on slot 3 is irq 9 */
<0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
<0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 9 */
/* IDSEL 6 */
<0x3000 0 0 1 &gpio0 10 3>, /* INT A on slot 3 is irq 10 */
<0x3000 0 0 2 &gpio0 9 3>, /* INT B on slot 3 is irq 9 */
<0x3000 0 0 3 &gpio0 8 3>, /* INT C on slot 3 is irq 8 */
<0x3000 0 0 4 &gpio0 11 3>, /* INT D on slot 3 is irq 11 */
<0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */
<0x3000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 9 */
<0x3000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 8 */
<0x3000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 11 */
/* IDSEL 15 */
<0x7800 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */
<0x7800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
<0x7800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
<0x7800 0 0 4 &gpio0 9 3>; /* INT D on slot 3 is irq 9 */
<0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
<0x7800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
<0x7800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
<0x7800 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 9 */
};
ethernet@c800a000 {

68
arch/arm/boot/dts/intel-ixp43x-kixrp435.dts Normal file
View File

@@ -0,0 +1,68 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Intel KIXRP435 Control Plane
* processor reference design.
*/
/dts-v1/;
#include "intel-ixp43x.dtsi"
#include "intel-ixp4xx-reference-design.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Intel KIXRP435 Reference Design";
compatible = "intel,kixrp435", "intel,ixp43x";
#address-cells = <1>;
#size-cells = <1>;
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 16 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x0fe0000 */
fis-index-block = <0x7f>;
};
};
};
/* CHECKME: ethernet set-up taken from Gateworks Cambria */
ethernet@c800a000 {
status = "ok";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
};
};
ethernet@c800c000 {
status = "ok";
queue-rx = <&qmgr 2>;
queue-txready = <&qmgr 19>;
phy-mode = "rgmii";
phy-handle = <&phy2>;
intel,npe-handle = <&npe 0>;
};
};
};

6
arch/arm/boot/dts/intel-ixp43x.dtsi
View File

@@ -8,6 +8,12 @@
/ {
soc {
bus@c4000000 {
compatible = "intel,ixp43x-expansion-bus-controller", "syscon";
/* Uses at least up to 0x230 */
reg = <0xc4000000 0x1000>;
};
pci@c0000000 {
compatible = "intel,ixp43x-pci";
};

11
arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
View File

@@ -9,6 +9,17 @@
/ {
soc {
bus@c4000000 {
compatible = "intel,ixp46x-expansion-bus-controller", "syscon";
/* Uses at least up to 0x124 */
reg = <0xc4000000 0x1000>;
};
rng@70002100 {
compatible = "intel,ixp46x-rng";
reg = <0x70002100 4>;
};
interrupt-controller@c8003000 {
compatible = "intel,ixp43x-interrupt";
};

38
arch/arm/boot/dts/intel-ixp46x-ixdp465.dts Normal file
View File

@@ -0,0 +1,38 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Intel IXDP465 Control Plane processor reference
* design, codename "BMP".
*/
/dts-v1/;
#include "intel-ixp45x-ixp46x.dtsi"
#include "intel-ixp4xx-reference-design.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Intel IXDP465 BMP Reference Design";
compatible = "intel,ixdp465", "intel,ixp46x";
#address-cells = <1>;
#size-cells = <1>;
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 32 MB of Flash mapped in at CS0 and CS1 */
reg = <0 0x00000000 0x2000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x1fe0000 */
fis-index-block = <0xff>;
};
};
};
/* TODO: configure ethernet etc */
};
};

132
arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi Normal file
View File

@@ -0,0 +1,132 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree include file for Intel reference designs for the
* XScale Network Processors in the IXP 4xx series. Common device
* set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465.
*/
/ {
memory@0 {
/*
* The board supports up to 256 MB of memory. Here we put in
* 64 MB and this may be modified by the boot loader.
*/
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@50 {
/*
* Philips PCF8582C-2T/03 512byte I2C EEPROM
* should behave like an Atmel 24c04.
*/
compatible = "atmel,24c04";
reg = <0x50>;
pagesize = <16>;
size = <512>;
read-only;
};
};
soc {
bus@c4000000 {
/* Flash memory defined per-variant */
nand-controller@3,0 {
/* Some designs have a NAND on CS3 enable it here if present */
status = "disabled";
/*
* gen_nand needs to be extended and documented to get
* command byte = 1 and address byte = 2 from the device
* tree.
*/
compatible = "gen_nand";
/* Expansion bus set-up */
intel,ixp4xx-eb-t1 = <0>;
intel,ixp4xx-eb-t2 = <0>;
intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase
intel,ixp4xx-eb-t4 = <0>;
intel,ixp4xx-eb-t5 = <0>;
intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
intel,ixp4xx-eb-byte-access-on-halfword = <0>;
intel,ixp4xx-eb-mux-address-and-data = <0>;
intel,ixp4xx-eb-ahb-split-transfers = <0>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
/* 512 bytes memory window */
reg = <3 0x00000000 0x200>;
nand-on-flash-bbt;
nand-ecc-mode = "soft_bch";
nand-ecc-step-size = <512>;
nand-ecc-strength = <4>;
nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */
label = "ixp400 NAND";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
fs@0 {
label = "ixp400 NAND FS 0";
reg = <0x0 0x800000>;
};
fs@800000 {
label = "ixp400 NAND FS 1";
reg = <0x800000 0x0>;
};
};
};
};
pci@c0000000 {
status = "ok";
/*
* Taken from IXDP425 PCI boardfile.
* PCI slots on the BIXMB425BD base card.
* We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
*/
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
<0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
<0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
<0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
/* IDSEL 3 */
<0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
<0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
/* IDSEL 4 */
<0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
<0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
};
};
};

44
arch/arm/boot/dts/intel-ixp4xx.dtsi
View File

@@ -15,16 +15,30 @@ soc {
interrupt-parent = <&intcon>;
/*
* The IXP4xx expansion bus is a set of 16 or 32MB
* windows in the 256MB space from 0x50000000 to
* 0x5fffffff.
* The IXP4xx expansion bus is a set of up to 7 each up to 16MB
* windows in the 256MB space from 0x50000000 to 0x5fffffff.
*/
bus@50000000 {
compatible = "simple-bus";
#address-cells = <1>;
bus@c4000000 {
/* compatible and reg filled in by per-soc device tree */
native-endian;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x00000000 0x50000000 0x10000000>;
dma-ranges = <0x00000000 0x50000000 0x10000000>;
ranges = <0 0x0 0x50000000 0x01000000>,
<1 0x0 0x51000000 0x01000000>,
<2 0x0 0x52000000 0x01000000>,
<3 0x0 0x53000000 0x01000000>,
<4 0x0 0x54000000 0x01000000>,
<5 0x0 0x55000000 0x01000000>,
<6 0x0 0x56000000 0x01000000>,
<7 0x0 0x57000000 0x01000000>;
dma-ranges = <0 0x0 0x50000000 0x01000000>,
<1 0x0 0x51000000 0x01000000>,
<2 0x0 0x52000000 0x01000000>,
<3 0x0 0x53000000 0x01000000>,
<4 0x0 0x54000000 0x01000000>,
<5 0x0 0x55000000 0x01000000>,
<6 0x0 0x56000000 0x01000000>,
<7 0x0 0x57000000 0x01000000>;
};
qmgr: queue-manager@60000000 {
@@ -83,6 +97,20 @@ uart0: serial@c8000000 {
no-loopback-test;
};
uart1: serial@c8001000 {
compatible = "intel,xscale-uart";
reg = <0xc8001000 0x1000>;
/*
* The reg-offset and reg-shift is a side effect
* of running the platform in big endian mode.
*/
reg-offset = <3>;
reg-shift = <2>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <14745600>;
no-loopback-test;
};
gpio0: gpio@c8004000 {
compatible = "intel,ixp4xx-gpio";
reg = <0xc8004000 0x1000>;