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arm64: dts: renesas: r9a07g054: Add DSI node

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Add DSI node to RZ/V2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230411100346.299768-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das
2023-04-11 11:03:44 +01:00
committed by Geert Uytterhoeven
parent 862b676c3c
commit 33de13da4e
1 changed files with 28 additions and 0 deletions
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28
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
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@@ -623,6 +623,34 @@ sbc: spi@10060000 {
status = "disabled";
};
dsi: dsi@10850000 {
compatible = "renesas,r9a07g054-mipi-dsi",
"renesas,rzg2l-mipi-dsi";
reg = <0 0x10850000 0 0x20000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "seq0", "seq1", "vin1", "rcv",
"ferr", "ppi", "debug";
clocks = <&cpg CPG_MOD R9A07G054_MIPI_DSI_PLLCLK>,
<&cpg CPG_MOD R9A07G054_MIPI_DSI_SYSCLK>,
<&cpg CPG_MOD R9A07G054_MIPI_DSI_ACLK>,
<&cpg CPG_MOD R9A07G054_MIPI_DSI_PCLK>,
<&cpg CPG_MOD R9A07G054_MIPI_DSI_VCLK>,
<&cpg CPG_MOD R9A07G054_MIPI_DSI_LPCLK>;
clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
resets = <&cpg R9A07G054_MIPI_DSI_CMN_RSTB>,
<&cpg R9A07G054_MIPI_DSI_ARESET_N>,
<&cpg R9A07G054_MIPI_DSI_PRESET_N>;
reset-names = "rst", "arst", "prst";
power-domains = <&cpg>;
status = "disabled";
};
vspd: vsp@10870000 {
compatible = "renesas,r9a07g054-vsp2",
"renesas,r9a07g044-vsp2";