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Merge tag 'hisi-arm32-dt-for-5.11' of git://github.com/hisilicon/linux-hisi into arm/dt

Browse Source 
ARM: DT: Hisilicon ARM32 DT updates for 5.11

- Cleanups of the hisilicon DTS to align with the dtschema including
  serial, usb, amba-bus, memory, mmc, spi and syscon. All of them do not
  have any functional effect except passing dtschema checks or dtc W=2
  builds.

* tag 'hisi-arm32-dt-for-5.11' of git://github.com/hisilicon/linux-hisi:
  ARM: dts: hisilicon: fix errors detected by syscon.yaml
  ARM: dts: hisilicon: fix errors detected by spi-pl022.yaml
  ARM: dts: hisilicon: fix errors detected by synopsys-dw-mshc.yaml
  ARM: dts: hisilicon: fix errors detected by root-node.yaml
  ARM: dts: hisilicon: fix errors detected by simple-bus.yaml
  ARM: dts: hisilicon: fix errors detected by usb yaml
  ARM: dts: hisilicon: fix errors detected by pl011.yaml
  ARM: dts: hisilicon: fix errors detected by snps-dw-apb-uart.yaml

Link: https://lore.kernel.org/r/5FBDC347.4050102@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2020-11-26 22:09:35 +01:00
parent c7cf673399 d48b6ef74a
commit 3319f1489e
10 changed files with 85 additions and 85 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/hi3519-demb.dts
View File

@@ -14,7 +14,7 @@ aliases {
serial0 = &uart0;
};
memory {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};

32
arch/arm/boot/dts/hi3519.dtsi
View File

@@ -52,8 +52,8 @@ uart0: serial@12100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12100000 0x1000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART0_CLK>;
clock-names = "apb_pclk";
clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>;
clock-names = "uartclk", "apb_pclk";
status = "disable";
};
@@ -61,8 +61,8 @@ uart1: serial@12101000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12101000 0x1000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART1_CLK>;
clock-names = "apb_pclk";
clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>;
clock-names = "uartclk", "apb_pclk";
status = "disable";
};
@@ -70,8 +70,8 @@ uart2: serial@12102000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12102000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART2_CLK>;
clock-names = "apb_pclk";
clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>;
clock-names = "uartclk", "apb_pclk";
status = "disable";
};
@@ -79,8 +79,8 @@ uart3: serial@12103000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12103000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART3_CLK>;
clock-names = "apb_pclk";
clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>;
clock-names = "uartclk", "apb_pclk";
status = "disable";
};
@@ -88,8 +88,8 @@ uart4: serial@12104000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12104000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART4_CLK>;
clock-names = "apb_pclk";
clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>;
clock-names = "uartclk", "apb_pclk";
status = "disable";
};
@@ -127,8 +127,8 @@ spi_bus0: spi@12120000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x12120000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_SPI0_CLK>;
clock-names = "apb_pclk";
clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>;
clock-names = "sspclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -139,8 +139,8 @@ spi_bus1: spi@12121000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x12121000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_SPI1_CLK>;
clock-names = "apb_pclk";
clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>;
clock-names = "sspclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -151,8 +151,8 @@ spi_bus2: spi@12122000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x12122000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_SPI2_CLK>;
clock-names = "apb_pclk";
clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>;
clock-names = "sspclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;

24
arch/arm/boot/dts/hi3620-hi4511.dts
View File

@@ -17,46 +17,46 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
amba {
amba-bus {
dual_timer0: dual_timer@800000 {
status = "ok";
};
uart0: uart@b00000 { /* console */
pinctrl-names = "default", "idle";
uart0: serial@b00000 { /* console */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;
status = "ok";
};
uart1: uart@b01000 { /* modem */
pinctrl-names = "default", "idle";
uart1: serial@b01000 { /* modem */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>;
status = "ok";
};
uart2: uart@b02000 { /* audience */
pinctrl-names = "default", "idle";
uart2: serial@b02000 { /* audience */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>;
status = "ok";
};
uart3: uart@b03000 {
pinctrl-names = "default", "idle";
uart3: serial@b03000 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>;
status = "ok";
};
uart4: uart@b04000 {
pinctrl-names = "default", "idle";
uart4: serial@b04000 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>;
status = "ok";

32
arch/arm/boot/dts/hi3620.dtsi
View File

@@ -63,7 +63,7 @@ cpu@3 {
};
};
amba {
amba-bus {
#address-cells = <1>;
#size-cells = <1>;
@@ -172,48 +172,48 @@ timer5: timer@600 {
interrupts = <1 13 0xf01>;
};
uart0: uart@b00000 {
uart0: serial@b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb00000 0x1000>;
interrupts = <0 20 4>;
clocks = <&clock HI3620_UARTCLK0>;
clock-names = "apb_pclk";
clocks = <&clock HI3620_UARTCLK0>, <&clock HI3620_UARTCLK0>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart1: uart@b01000 {
uart1: serial@b01000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb01000 0x1000>;
interrupts = <0 21 4>;
clocks = <&clock HI3620_UARTCLK1>;
clock-names = "apb_pclk";
clocks = <&clock HI3620_UARTCLK1>, <&clock HI3620_UARTCLK1>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart2: uart@b02000 {
uart2: serial@b02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb02000 0x1000>;
interrupts = <0 22 4>;
clocks = <&clock HI3620_UARTCLK2>;
clock-names = "apb_pclk";
clocks = <&clock HI3620_UARTCLK2>, <&clock HI3620_UARTCLK2>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart3: uart@b03000 {
uart3: serial@b03000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb03000 0x1000>;
interrupts = <0 23 4>;
clocks = <&clock HI3620_UARTCLK3>;
clock-names = "apb_pclk";
clocks = <&clock HI3620_UARTCLK3>, <&clock HI3620_UARTCLK3>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart4: uart@b04000 {
uart4: serial@b04000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb04000 0x1000>;
interrupts = <0 24 4>;
clocks = <&clock HI3620_UARTCLK4>;
clock-names = "apb_pclk";
clocks = <&clock HI3620_UARTCLK4>, <&clock HI3620_UARTCLK4>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};

2
arch/arm/boot/dts/hip01-ca9x2.dts
View File

@@ -37,7 +37,7 @@ cpu@1 {
};
};
memory {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};

26
arch/arm/boot/dts/hip01.dtsi
View File

@@ -35,47 +35,47 @@ soc {
interrupt-parent = <&gic>;
ranges = <0 0x10000000 0x20000000>;
amba {
amba-bus {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
uart0: uart@10001000 {
uart0: serial@10001000 {
compatible = "snps,dw-apb-uart";
reg = <0x10001000 0x1000>;
clocks = <&hisi_refclk144mhz>;
clock-names = "apb_pclk";
clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
interrupts = <0 32 4>;
status = "disabled";
};
uart1: uart@10002000 {
uart1: serial@10002000 {
compatible = "snps,dw-apb-uart";
reg = <0x10002000 0x1000>;
clocks = <&hisi_refclk144mhz>;
clock-names = "apb_pclk";
clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
interrupts = <0 33 4>;
status = "disabled";
};
uart2: uart@10003000 {
uart2: serial@10003000 {
compatible = "snps,dw-apb-uart";
reg = <0x10003000 0x1000>;
clocks = <&hisi_refclk144mhz>;
clock-names = "apb_pclk";
clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
interrupts = <0 34 4>;
status = "disabled";
};
uart3: uart@10006000 {
uart3: serial@10006000 {
compatible = "snps,dw-apb-uart";
reg = <0x10006000 0x1000>;
clocks = <&hisi_refclk144mhz>;
clock-names = "apb_pclk";
clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
interrupts = <0 4 4>;
status = "disabled";

2
arch/arm/boot/dts/hip04-d01.dts
View File

@@ -22,7 +22,7 @@ memory@0,10000000 {
};
soc {
uart0: uart@4007000 {
uart0: serial@4007000 {
status = "ok";
};
};

6
arch/arm/boot/dts/hip04.dtsi
View File

@@ -250,12 +250,12 @@ arm-pmu {
<0 79 4>;
};
uart0: uart@4007000 {
uart0: serial@4007000 {
compatible = "snps,dw-apb-uart";
reg = <0x4007000 0x1000>;
interrupts = <0 381 4>;
clocks = <&clk_168m>;
clock-names = "uartclk";
clocks = <&clk_168m>, <&clk_168m>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
status = "disabled";
};

2
arch/arm/boot/dts/hisi-x5hd2-dkb.dts
View File

@@ -35,7 +35,7 @@ cpu@1 {
};
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x80000000>;
};

42
arch/arm/boot/dts/hisi-x5hd2.dtsi
View File

@@ -30,7 +30,7 @@ soc {
interrupt-parent = <&gic>;
ranges = <0 0xf8000000 0x8000000>;
amba {
amba-bus {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -86,48 +86,48 @@ timer4: timer@a81000 {
status = "disabled";
};
uart0: uart@b00000 {
uart0: serial@b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00b00000 0x1000>;
interrupts = <0 49 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart1: uart@6000 {
uart1: serial@6000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00006000 0x1000>;
interrupts = <0 50 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart2: uart@b02000 {
uart2: serial@b02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00b02000 0x1000>;
interrupts = <0 51 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart3: uart@b03000 {
uart3: serial@b03000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00b03000 0x1000>;
interrupts = <0 52 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart4: uart@b04000 {
uart4: serial@b04000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb04000 0x1000>;
interrupts = <0 53 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
@@ -423,7 +423,7 @@ mmc: mmc@1830000 {
interrupts = <0 35 4>;
clocks = <&clock HIX5HD2_MMC_CIU_RST>,
<&clock HIX5HD2_MMC_BIU_CLK>;
clock-names = "ciu", "biu";
clock-names = "biu", "ciu";
};
sd: mmc@1820000 {
@@ -432,7 +432,7 @@ sd: mmc@1820000 {
interrupts = <0 34 4>;
clocks = <&clock HIX5HD2_SD_CIU_RST>,
<&clock HIX5HD2_SD_BIU_CLK>;
clock-names = "ciu","biu";
clock-names = "biu", "ciu";
};
gmac0: ethernet@1840000 {
@@ -453,14 +453,14 @@ gmac1: ethernet@1841000 {
status = "disabled";
};
usb0: ehci@1890000 {
usb0: usb@1890000 {
compatible = "generic-ehci";
reg = <0x1890000 0x1000>;
interrupts = <0 66 4>;
clocks = <&clock HIX5HD2_USB_CLK>;
};
usb1: ohci@1880000 {
usb1: usb@1880000 {
compatible = "generic-ohci";
reg = <0x1880000 0x1000>;
interrupts = <0 67 4>;
@@ -468,7 +468,7 @@ usb1: ohci@1880000 {
};
peripheral_ctrl: syscon@a20000 {
compatible = "syscon";
compatible = "hisilicon,peri-subctrl", "syscon";
reg = <0xa20000 0x1000>;
};