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arm64: dts: hi3798cv200: enable PCIe support for poplar board

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It adds combophy devices under peripheral controller and enables PCIe
support for Hi3798CV200 Poplar board.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This commit is contained in:
Shawn Guo
2018-05-11 10:03:38 +08:00
committed by Wei Xu
parent d2a1606c29
commit 32fa01761b
2 changed files with 78 additions and 0 deletions
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15
arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
View File

@@ -61,6 +61,15 @@ user-led3 {
default-state = "off";
};
};
reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
regulator-name = "3V3_PCIE0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio6 7 0>;
enable-active-high;
};
};
&gmac1 {
@@ -146,6 +155,12 @@ &ir {
status = "okay";
};
&pcie {
reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
vpcie-supply = <&reg_pcie>;
status = "okay";
};
&sd0 {
bus-width = <4>;
cap-sd-highspeed;

63
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
View File

@@ -8,7 +8,9 @@
*/
#include <dt-bindings/clock/histb-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/ti-syscon.h>
/ {
@@ -106,6 +108,37 @@ sysctrl: system-controller@8000000 {
#reset-cells = <2>;
};
perictrl: peripheral-controller@8a20000 {
compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
"simple-mfd";
reg = <0x8a20000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x8a20000 0x1000>;
combphy0: phy@850 {
compatible = "hisilicon,hi3798cv200-combphy";
reg = <0x850 0x8>;
#phy-cells = <1>;
clocks = <&crg HISTB_COMBPHY0_CLK>;
resets = <&crg 0x188 4>;
assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
assigned-clock-rates = <100000000>;
hisilicon,fixed-mode = <PHY_TYPE_USB3>;
};
combphy1: phy@858 {
compatible = "hisilicon,hi3798cv200-combphy";
reg = <0x858 0x8>;
#phy-cells = <1>;
clocks = <&crg HISTB_COMBPHY1_CLK>;
resets = <&crg 0x188 12>;
assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
assigned-clock-rates = <100000000>;
hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
};
};
uart0: serial@8b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b00000 0x1000>;
@@ -419,5 +452,35 @@ ir: ir@8001000 {
clocks = <&sysctrl HISTB_IR_CLK>;
status = "disabled";
};
pcie: pcie@9860000 {
compatible = "hisilicon,hi3798cv200-pcie";
reg = <0x9860000 0x1000>,
<0x0 0x2000>,
<0x2000000 0x01000000>;
reg-names = "control", "rc-dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0 15>;
num-lanes = <1>;
ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_PCIE_AUX_CLK>,
<&crg HISTB_PCIE_PIPE_CLK>,
<&crg HISTB_PCIE_SYS_CLK>,
<&crg HISTB_PCIE_BUS_CLK>;
clock-names = "aux", "pipe", "sys", "bus";
resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
reset-names = "soft", "sys", "bus";
phys = <&combphy1 PHY_TYPE_PCIE>;
phy-names = "phy";
status = "disabled";
};
};
};