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drm/xe/dg2: Wa_18028616096 now applies to all DG2

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The workaround database was just updated to extend this workaround to
DG2-G11 (whereas previously it applied only to G10 and G12).

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20231115183029.2649992-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper
2023-11-15 10:30:30 -08:00
committed by Rodrigo Vivi
parent aaa115ffaa
commit 32dd40fb48
1 changed files with 1 additions and 6 deletions
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7
drivers/gpu/drm/xe/xe_wa.c
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@@ -403,12 +403,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
PERF_FIX_BALANCING_CFE_DISABLE))
},
{ XE_RTP_NAME("18028616096"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
},
{ XE_RTP_NAME("18028616096"),
XE_RTP_RULES(SUBPLATFORM(DG2, G12),
XE_RTP_RULES(PLATFORM(DG2),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
},