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wifi: rtw89: pci: no need to wait CLK ready for RTL8922DE

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The bit is to wait for CLK ready when entering PCIE L1SS. However, a
certain host might not enable CLK for a situation, causing device state
stuck and trigger PCIE SER. Unset this bit as default like earlier chips.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260424072552.59220-2-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
2026-04-24 15:25:50 +08:00
parent 6d88244bb1
commit 329e9fff98
2 changed files with 14 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/wireless/realtek/rtw89/pci.h
View File

@@ -33,6 +33,8 @@
#define RAC_REG_REV2 0x1B
#define BAC_CMU_EN_DLY_MASK GENMASK(15, 12)
#define PCIE_DPHY_DLY_25US 0x1
#define RAC_ANA14 0x14
#define EIEOS_L1SS_WAIT_CLKRDY BIT(2)
#define RAC_ANA19 0x19
#define B_PCIE_BIT_RD_SEL BIT(2)
#define RAC_REG_FLD_0 0x1D

12
drivers/net/wireless/realtek/rtw89/pci_be.c
View File

@@ -83,6 +83,17 @@ static void _patch_pcie_power_wake_be(struct rtw89_dev *rtwdev, bool power_up)
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, BIT_WAKE_CTRL_V1);
}
static void _patch_pre_init_be(struct rtw89_dev *rtwdev)
{
struct rtw89_hal *hal = &rtwdev->hal;
if (!(rtwdev->chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7090))
return;
rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G2 +
RAC_ANA14 * RAC_MULT, EIEOS_L1SS_WAIT_CLKRDY);
}
static void rtw89_pci_set_io_rcy_be(struct rtw89_dev *rtwdev)
{
const struct rtw89_pci_info *info = rtwdev->pci_info;
@@ -475,6 +486,7 @@ static int rtw89_pci_ops_mac_pre_init_be(struct rtw89_dev *rtwdev)
rtw89_pci_set_io_rcy_be(rtwdev);
_patch_pcie_power_wake_be(rtwdev, true);
_patch_pre_init_be(rtwdev);
rtw89_pci_ctrl_wpdma_pcie_be(rtwdev, false);
rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_DISABLE,
MAC_AX_PCIE_DISABLE, MAC_AX_PCIE_DISABLE);