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drm/i915/dsb: Align DSB register writes to 8 bytes

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Every DSB instruction has to be 8byte aligned. Make sure
that is the case for the non-indexed register writes as well.
The way this could end up unaligned is we emitted an odd
number of indexed register writes beforehand.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221216003810.13338-4-ville.syrjala@linux.intel.com
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
This commit is contained in:
Ville Syrjälä
2022-12-16 02:38:00 +02:00
parent f9e2ada6fe
commit 3229319e44
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/i915/display/intel_dsb.c
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@@ -172,6 +172,9 @@ void intel_dsb_reg_write(struct intel_dsb *dsb,
return;
}
/* Every instruction should be 8 byte aligned. */
dsb->free_pos = ALIGN(dsb->free_pos, 2);
dsb->ins_start_offset = dsb->free_pos;
buf[dsb->free_pos++] = val;
buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |