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drm/amdgpu/gfx12: remove GDS leftovers
GDS doesn't exist in gfx12. The incomplete packet allows userspace to hang the hw from the kernel. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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committed by
Alex Deucher
parent
e5f6bfe402
commit
30fb9cad6f
@@ -4108,21 +4108,6 @@ static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
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/* inherit vmid from mqd */
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control |= 0x40000000;
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/* Currently, there is a high possibility to get wave ID mismatch
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* between ME and GDS, leading to a hw deadlock, because ME generates
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* different wave IDs than the GDS expects. This situation happens
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* randomly when at least 5 compute pipes use GDS ordered append.
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* The wave IDs generated by ME are also wrong after suspend/resume.
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* Those are probably bugs somewhere else in the kernel driver.
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*
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* Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
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* GDS to 0 for this ring (me/pipe).
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*/
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if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
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amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
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}
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amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
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BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
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amdgpu_ring_write(ring,
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@@ -4721,7 +4706,6 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = {
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SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
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2 + /* VM_FLUSH */
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8 + /* FENCE for VM_FLUSH */
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20 + /* GDS switch */
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5 + /* COND_EXEC */
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7 + /* HDP_flush */
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4 + /* VGT_flush */
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